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Exploring Parallelism in ZynqNet AI Engine to Accelerate Image Classification in Aerospace

Exploring Parallelism in ZynqNet AI Engine to Accelerate Ima...

引用

IEEE Latin American Symposium on Circuits and Systems (LASCAS)

作者： Eduardo Marañon Aguilar Fabio Benevenuti Fernanda Lima Kastensmidt Federal University of Rio Grande do Sul (UFRGS) Institute of Informatics Microelectronics Graduate Program (PGMICRO) Porto Alegre Brazil

ISBN: (数字)9798331522124

ISBN: (纸本)9798331522131

This research investigates various configurations of the Zynqnet AI Engine to accelerate image classification tasks using the SAT-6 dataset and a 4-layer CNN. The C++ code for the hardware accelerator was translated into RTL using Vivado HLS and integrated with the Zynq Processing System on a ZedBoard Zynq-7000 ARM/FPGA SoC. The AI engine was configured to work with 32 -bit floating point, 8bit fixed point and 8 -bit integer type operations, with different processing elements for parallelizing CNN tasks. Given a 64-bit data memory bus in communication with the accelerator and an 8-bit integer quantization, the variation in the number of processing elements does not result in a significant performance improvement. To address this, 8 values were grouped for reading and writing in 64-bit parallel mode, and different communication architectures were designed to improve data transfer between the accelerator and DDR memory, with optional enablement of L1D and L2 cache. The research analyzes CNN computation performance and FPGA resource usage (LUTs, FFs, BRAMs, DSPs) across configurations, providing insights into the trade-offs in FPGA-based CNN implementations, aiding the development of efficient, high-performance hardware accelerators for Deep Learning applications.

关键词： Quantization (signal) Writing Table lookup System-on-chip Convolutional neural networks Artificial intelligence Hardware acceleration Engines Field programmable gate arrays Image classification

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Hardening a RISC-V Softcore for Embedded Aerospace Applications in SRAM-based FPGA

Hardening a RISC-V Softcore for Embedded Aerospace Applicati...

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Symposium on Integrated Circuits and Systems Design (SBCCI)

作者： Eduardo Marañon Aguilar Fabio Benevenuti Fernanda Lima Kastensmidt Institute of Informatics Microelectronics Graduate Program (PGMICRO) Federal University of Rio Grande do Sul (UFRGS) Porto Alegre Brazil

ISBN: (数字)9798350391695

ISBN: (纸本)9798350391701

We investigate the implementation of triple modular redundancy (TMR) with different number of voters in a softcore RISC-V microprocessor to mitigate radiation-induced faults in the configuration memory (CRAM) of SRAM-based FPGA. The case-study microprocessor is the Steel Core implemented in AMD Xilinx 7-Series/Zynq-7000 device, executing benchmark software on the FreeRTOS operating system. We implemented coarse-grained TMR (CGTMR) and fine-grained distributed TMR (FGDTMR) using an automated redundancy and voter insertion tool. TMR is used in combination with memory scrubber featured by the FPGA hardware, which uses error correction codes (ECC) to revert radiation-induced faults in CRAM. Fault injection in CRAM emulating radiation-induced faults is used to evaluate the benefits of both TMR and ECC. Under fault injection, combining the fault masking capability of TMR with the self-healing by ECC, improved mean time between failures (MTBF) up to 5×. ECC alone did not improve significantly the fault tolerance. Without ECC, FGDTMR improves MTBF in 2×, but at a higher cost in circuit area and resources usage. When combined with ECC, the CGTMR provides fault tolerance comparable to FGDTMR but with 30% less resources usage.

关键词： Prevention and mitigation Microprocessors Redundancy Fault tolerant systems Software Error correction codes Software reliability Circuit faults Steel Field programmable gate arrays

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VLSI Design of Tree-Based Inference for Low-Power Learning Applications

VLSI Design of Tree-Based Inference for Low-Power Learning A...

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Brunno A. Abreu Mateus Grellert Sergio Bampi Graduate Program in Microelectronics (PGMICRO) INF-UFRGS Federal University of Rio Grande do Sul Porto Alegre Brazil Department of Informatics and Statistics − INE Federal University of Santa Catarina (UFSC) Florianópolis Brazil Graduate Program on Electronic Engineering and Computing Catholic University of Pelotas (UCPel) Pelotas Brazil

ISBN: (数字)9781728133201

ISBN: (纸本)9781728133218

The use of Machine Learning techniques in battery-powered devices has increased in recent years. Therefore, evaluating power-accuracy trade-offs of inference models has become important. This work explores decision trees architectures, analyzing the effects of model complexity and approximation in power and accuracy. By quantizing the inputs to limited widths, we increased the accuracy of the models in up to 8.7% compared to precise cases. In terms of power, the variation in model complexity was more significant than in input width, as we obtained reductions of up to 97% by decreasing the tree depth, compared to 88% when decreasing the width.

关键词： Complexity theory Hardware Integrated circuit modeling Training Analytical models Decision trees Quantization (signal)

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Within-die and die-to-die variability on 65nm CMOS : Oscillators experimental results 6

Within-die and die-to-die variability on 65nm CMOS : Oscilla...

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6th International Workshop on CMOS Variability, VARI 2015

作者： Brito, Juan Pablo Martinez Lubaszewski, Marcelo Bampi, Sergio Graduate Program on Microelectronics PGMICRO - Informatics Institute Federal University of Rio Grande do Sul UFRGS Porto Alegre Brazil CEITEC S.A. Semiconductors Porto Alegre Brazil

ISBN: (纸本)9781509000715

This paper presents experimental data and analyses from the oscillation frequency of CMOS ring oscillators (ROs). The measurements are analyzed in order to separate the coefficient of variation (CV = σ/μ) behavior of both within-die (WID) process variations and Die-to-Die (D2D) process variations. Three different RO's sizes distributed over a total of 96 ROs per chip were measured in 32 different chip samples, all from a single MOSIS Multi-Project-wafer in a commercial 65nm CMOS process. All ROs were measured with varying power supply voltages, from nominal VDD (1.2V) down to nearthreshold (0.45V), resulting in a sample space of 18.432 points of interest. Statistical analysis results are shown regarding each RO stage size, the applied power supply and the correlation of both to the WID and D2D variations. The increase on D2D and WID coefficients of variations at the near-threshold supplies is very significant, as explained by increased delay variability at the moderate inversion regime of the FETs. The 96 test ROs occupy a total area of 200 x 480 μm2 in each test chip. © 2015 IEEE.

关键词： Dies

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MOSFET stacked-pair test structure for mismatch evaluation by estimating the on-resistance ratio 6

MOSFET stacked-pair test structure for mismatch evaluation b...

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6th International Workshop on CMOS Variability, VARI 2015

作者： Brito, Juan Pablo Martinez Lubaszewski, Marcelo Bampi, Sergio Graduate Program on Microelectronics PGMICRO - Informatics Institute Federal University of Rio Grande do Sul - UFRGS Porto Alegre Brazil CEITEC S.A. Semiconductors Porto Alegre Brazil

ISBN: (纸本)9781509000715

This work describes a procedure for evaluating the mismatch between MOSFET transistors in a test array and connected as stacked-pairs. The transistor mismatch is characterized by measuring the gate voltage dependence of the DC voltage established at the middle node of the common-gate MOSFET stacked-pair. This procedure is modeled as the onresistance ratio of these two transistors and it is performed by two simple measurements. Various pieces of information on the MOSFET mismatch characteristics (e.g., channel length variation and threshold voltage variation) can be extracted. The test structure was manufactured in 180nm CMOS technology, and the test array was designed to allow a large number of MOSFET stacked-pairs, from transistors placed in different parts of the layout to vary gradually the distance of the paired FETs. © 2015 IEEE.

关键词： Threshold voltage

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Within-die and die-to-die variability on 65nm CMOS : oscillators experimental results

Within-die and die-to-die variability on 65nm CMOS : oscilla...

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European Workshop on CMOS Variability (VARI)

作者： Juan Pablo Martinez Brito Marcelo Lubaszewski Sergio Bampi CEITEC S.A. Semiconductors Porto Alegre Brazil Graduate Program on Microelectronics - PGMICRO - Informatics Institute Federal University of Rio Grande do Sul- UFRGS

关键词： Frequency measurement Ring oscillators Semiconductor device measurement Inverters Transistors CMOS integrated circuits Standards

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Near-threshold computing for very wide frequency scaling: Approximate adders to rescue performance

Near-threshold computing for very wide frequency scaling: Ap...

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Annual IEEE Northeast Workshop on Circuits and Systems (NEWCAS)

作者： L. B. Soares Sergio Bampi A. L. R. Rosa E. A. C. Costa Graduate Program on Microelectronics (PGMicro) PPGC - Informatics Institute Federal University of Rio Grande do Sul (UFRGS) Catholic University of Pelotas (UCPEL) Porto Alegre Brazil

Near-threshold computing in CMOS is a promising alternative for any application which can tolerate very wide voltage-frequency scaling (VFS). Internet-of-Things (IoT) devices will operate in very different power-performance modes, from sub-MHz to peaks of hundreds of MHz. The nano-power range which is achievable in deca-nanometer CMOS at near-VT is the alternative we explore for VLSI circuits (8051 processor, filters, and ISCAS benchmark circuits). This paper proposes a method to design CMOS circuits for a wide dynamic range of VFS, and targets near-threshold for best efficiency. A standard-cell based design methodology specific for near-VT is demonstrated here in for a commercial 65nm CMOS process. Power and timing variability are characterized, so that variation-aware and yet ultra-low supply voltage designs are enabled. Our cell design method avoids unnecessary upsizing and it focus on near- and well above threshold regions of operation. For the study cases of medium complexity notch filter design (24kgates), and an 8051 compatible core (20kgates) we demonstrate 63X to 77X energy/operation savings for applications that tolerate ultra-wide frequency scaling (from hundreds of KHz to 1GHz) in their operating modes. The results were obtained using the minimal cycle time achievable at each supply voltage. The extremely low and highly-variable performance at sub- and near-VT have to be addressed by new logic design paradigms. In this paper we also exploit the use of approximate adders to increase the timing performance of a class of digital filter circuits, to enable compensating the performance loss inherent to near-VT operation in CMOS. Our results show that the effort to explore energy savings in low power optimized circuits through the approximate computing approach is validated with energy and worst path delay reductions up to 19.4% and 36.7% respectively, compared to the precise arithmetic implementation, without compromising the filters frequency response. Our a

关键词： Finite impulse response filters Adders CMOS integrated circuits Libraries Approximation methods Energy efficiency Timing

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Numerical analysis of the harmonics influence on linear interpolation for Power Quality assessment

Numerical analysis of the harmonics influence on linear inte...

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International Conference on Harmonics and Quality of Power

作者： Cesar David Paredes Crovato Leonardo Bandeira Soares Sergio Bampi Electrical Engineering Graduate Program-PPGEE Feevale University Unisinos University Novo Hamburgo/Sao Lepoldo Brazil Microelectronics Graduate Program-PGMicro-Informatics Federal University of Rio Grande do Sul-UFRGS Porto Alegre Brazil

This paper presents a numerical analysis to determine the minimum sampling frequency for which a linear interpolation of AC Power signals can be reliably used in the digital domain, regarding the harmonics influence for Power Quality (PQ) assessment. The proposed approach of this paper is based on exhaustive simulations which take into account a large combination of distinct values for module and phase of the third and fifth harmonic components at a given range of sampling frequencies. Our results show that the linear interpolation produces spectrum module errors up to 33.38% for a sampling frequency of 250/32 kHz, while the module percentage error is up to 2.08% at 250/4 kHz. The main contribution of this work is to best determine the minimum sampling frequency that can be used, considering the presence of harmonics components, which makes the linear interpolation an efficient technique for PQ assessment. A minimum sampling frequency turns out to be advantageous for the digital signal processing performance and cost.

关键词： Harmonic analysis Interpolation IEC standards Power system harmonics Power quality Electromagnetic compatibility

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A fast EMD-based technique for Power Quality signals decomposition, compression, and time-frequency analysis

A fast EMD-based technique for Power Quality signals decompo...

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International Conference on Digital Signal Processing (DSP)

作者： Leonardo Bandeira Soares Sergio Bampi Cesar David Paredes Crovato Informatics Institute-Microelectronics Graduate Program (PGMicro) Federal University of Rio Grande do Sul Porto Alegre Brazil ICET/PPGE Feevale Univ. São Leopoldo Brazil

In this paper an EMD-based (Empirical Mode Decomposition) technique is proposed in order to improve the data compression and reconstructed signal accuracy trade-off for PQ (Power Quality) signals. We demonstrate that our technique saves computational cost and reduces the mode mixing problem when compared to the EEMD (Ensemble EMD) and traditional EMD, respectively. After simulations with recorded power line test-cases, we compare our results with DWT (Discrete Wavelet Transform), and both traditional and EEMD. Results have shown that our technique outperforms the DWT in both data compression ratio and reconstruction accuracy metrics. Moreover, we analyze the balance between computational costs and mode mixing reduction for the three EMD techniques.

关键词： Discrete wavelet transforms Computational efficiency Accuracy Time-frequency analysis Wavelet analysis Splines (mathematics)

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