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Symposium on Integrated Circuits and Systems Design (SBCCI)

作者： Rafael Da Silva Mateus Grellert Ricardo Reis Graduate Program in Microelectronics - PGMICRO Federal University of Rio Grande do Sul - UFRGS Brazil

The advances in current video encoders allow significant compression at the cost of increased computing and energy consumption. This creates a demand for the development of dedicated accelerators that efficiently explore the parallelism of computing-intensive encoding operations. This work presents a hardware accelerator for the interpolation step of Versatile Video Coding (VVC) systems using Lower-Part-OR Adders (LOA). Unlike competing solutions, the proposed design fully complies with current VVC interpolation types, including the alternative filter of this standard. A data gating mechanism is also implemented to prevent unnecessary circuit switching. Experimental results show that savings of up to 78.51 % in power and 67.08% in gate count can be achieved by using approximate computing techniques.

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Quality-Reconfigurable Approximate Multiplier Utilizing Select Leading One-Bit Blocks

Quality-Reconfigurable Approximate Multiplier Utilizing Sele...

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IEEE Latin American Symposium on Circuits and Systems (LASCAS)

作者： João M. Bedin Pedro T. L. Pereira Rodrigo N. Wuerdig Eduardo Da Costa Sergio Bampi Graduate Program in Microelectronics (PGMicro) - Federal University of Rio Grande do Sul (UFRGS) Porto Alegre Brazil Graduate Program in Electronic Engineering and Computing - Catholic University of Pelotas (UCPel) Pelotas Brazil

ISBN: (数字)9798331522124

ISBN: (纸本)9798331522131

Multipliers are essential for emerging technologies, as they are vital arithmetic circuits in many energy-efficient applications, such as digital signal processing and machine learning applications. Approximate multipliers (AxM) became an optimal option for applications in ASIC systems with error tolerance. This paper proposes to develop a run-time reconfigurable AxM with four approximation levels in a single circuit, evaluating accuracy and circuit metrics (e.g., circuit area, timing, and power consumption) based on the leading one-bit-based approximate (LoBA) multiplier. The results achieve a circuit area reduction of 52% less area and up to 27% less power consumption when compared with equivalent architecture based on LoBA state-of-art. Applying the proposed RLoBA to a normalized least mean square (NLMS) adaptive filter case study, we obtain 22.95% less power consumption using dynamic approximate level selection than the precise multiplier while maintaining the same accuracy level.

关键词： Measurement Power demand Accuracy Circuits Adaptive filters Machine learning Lead Timing Reconfigurable architectures Standards

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Hardening a RISC-V Softcore for Embedded Aerospace Applications in SRAM-based FPGA

Hardening a RISC-V Softcore for Embedded Aerospace Applicati...

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Symposium on Integrated Circuits and Systems Design (SBCCI)

作者： Eduardo Marañon Aguilar Fabio Benevenuti Fernanda Lima Kastensmidt Institute of Informatics Microelectronics Graduate Program (PGMICRO) Federal University of Rio Grande do Sul (UFRGS) Porto Alegre Brazil

ISBN: (数字)9798350391695

ISBN: (纸本)9798350391701

We investigate the implementation of triple modular redundancy (TMR) with different number of voters in a softcore RISC-V microprocessor to mitigate radiation-induced faults in the configuration memory (CRAM) of SRAM-based FPGA. The case-study microprocessor is the Steel Core implemented in AMD Xilinx 7-Series/Zynq-7000 device, executing benchmark software on the FreeRTOS operating system. We implemented coarse-grained TMR (CGTMR) and fine-grained distributed TMR (FGDTMR) using an automated redundancy and voter insertion tool. TMR is used in combination with memory scrubber featured by the FPGA hardware, which uses error correction codes (ECC) to revert radiation-induced faults in CRAM. Fault injection in CRAM emulating radiation-induced faults is used to evaluate the benefits of both TMR and ECC. Under fault injection, combining the fault masking capability of TMR with the self-healing by ECC, improved mean time between failures (MTBF) up to 5×. ECC alone did not improve significantly the fault tolerance. Without ECC, FGDTMR improves MTBF in 2×, but at a higher cost in circuit area and resources usage. When combined with ECC, the CGTMR provides fault tolerance comparable to FGDTMR but with 30% less resources usage.

关键词： Prevention and mitigation Microprocessors Redundancy Fault tolerant systems Software Error correction codes Software reliability Circuit faults Steel Field programmable gate arrays

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An Optimized VLSI Exponential Unit Design Exploring Efficient Arithmetic Operation Strategies

An Optimized VLSI Exponential Unit Design Exploring Efficien...

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IEEE International Conference on Electronics, Circuits and Systems (ICECS)

作者： Patrícia Da Costa Morgana Da Rosa Rafael Soares Eduardo Da Costa Sergio Bampi Graduate Program on Microelectronics Federal University of Rio Grande do Sul Porto Alegre Brazil Graduate Program on Computing Federal University of Pelotas (UFPel) Pelotas Brazil Graduate Program on Electronic Engineering and Computing Catholic University of Pelotas (UCPel) Pelotas Brazil Graduate Program on Microelectronics (PGMICRO) Federal University of Rio Grande do Sul (UFRGS) Porto Alegre Brazil

This work presents an optimized exponential function VLSI hardware design by Taylor series expansion. The proposed architecture implements the exponential by approximating the logic design of a 4 th -order Taylor series and explores efficient CMOS arithmetic operation strategies. It implements a shift-based divider and explores an efficient 4-2 adder compressor in the adder tree. The proposal with a −7 to 11 input values range shows an output error of around 2% of MRED with a reduced energy consumption of 3.63 pJ/operation for 32-bit output. For a 64-bit output, the energy per operation of the VLSI exponential unit is 14.97pJ/op, being able to process a more comprehensive input range (i.e., −14 to 22) for a negligible mean output error of around 1.7% of MRED.

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LEX - A Cell Switching Arcs Extractor: A Simple SPICE-Input Interface for Electrical Characterization

LEX - A Cell Switching Arcs Extractor: A Simple SPICE-Input ...

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IEEE Computer Society Annual Symposium on VLSI

作者： Rodrigo N. Wuerdig Vitor H. Maciel Ricardo Reis Sergio Bampi Graduate Program in Microelectronics (PGMICRO) Universidade Federal do Rio Grande do Sul (UFRGS) Porto Alegre Brazil

The characterization of logic cells is a critical step in the design of digital circuits. Existing open-source cell characterization tools typically require significant extra information beyond the SPICE netlist. In this paper, we present a new open-source tool - LEX - that serves as a very useful interface for these characterization tools, enabling the extraction of essential input and output information, Boolean expressions, truth tables, and transition (switching) arcs directly from the SPICE netlist. Our LEX tool offers several advantages over existing open-source methods. First, it simplifies the cell electrical characterization process by eliminating the need for manual input of additional information. This saves time and reduces the incidence of errors. Second, our tool provides a more comprehensive set of information than existing tools, including Boolean expressions and truth tables. Third, LEX is highly flexible and can be integrated with a wide range of existing open-source cell characterization tools. We conducted experiments using a test set of netlists to demonstrate LEX effectiveness. By providing a more comprehensive set of information, eliminating the need for manual input of additional information, and improving efficiency, our tool offers a powerful new option to be integrated into already existing and future open-source characterization tools.

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CIMulator: Evaluating Neuromorphic Accelerators with HZO FefinFET-Based Synaptic Device 7

CIMulator: Evaluating Neuromorphic Accelerators with HZO Fef...

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7th International Conference on Green Technology and Sustainable Development, GTSD 2024

作者： Le, Hoang-Hiep Lu, Hao-Yu Baig, Md. Aftab De, Sourav Lin, Ing-Chao Lu, Darsen D. Minghsin University of Science and Technology Department of Computer Science and Information Engineering Hsinchu Taiwan National ChengKung University Intelligent Computing Industrial Doctorate Program Tainan Taiwan Institute of Microelectronics National ChengKung University Tainan Taiwan National ChengKung University Department of Computer Science and Information Engineering Tainan Taiwan

ISBN: (纸本)9798350386073

In this study, we use the CIMulator platform to evaluate the performance of neuromorphic accelerators with novel Hf0.5Zr0.5O2 (HZO) ferroelectric fin field-effect transistor (FefinFET) as synaptic device. The MNIST handwritten digit dataset is used for training and inference processes in multilayer perceptron (MLP) neural networks. With the highly optimized synaptic device, the results demonstrate high training and inference accuracy, achieving up to 97% for the MLP, approaching the accuracy of software implementations. © 2024 IEEE.

关键词： Multilayer neural networks

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Surface Characterization of Sodium Cholate Treated CVD Graphene

Surface Characterization of Sodium Cholate Treated CVD Graph...

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IEEE Conference on Nanotechnology

作者： Evans Addo-Mensah Janet Obaemo Katie Welch Yang Tian Shiva Dolatabadi Hugh Churchill Uchechukwu Wejinya Materials Science and Engineering Graduate Program University of Arkansas Microelectronics and Photonics Program University of Arkansas Department of Physics University of Arkansas Fayetteville Arkansas Department of Mechanical Engineering University of Arkansas Fayetteville Arkansas

The advancement of graphene has created a need in exploring its properties for different applications. One way to explore its properties is by reducing its hydrophobicity. To overcome hydrophobicity of graphene, surfactants have been used in functionalization, hence improving the surface properties of the graphene monolayer. Therefore, investigating surfactant treatment for CVD graphene becomes useful in understanding the surface property effects on graphene. This study utilizes CVD graphene on silicon substrates. Its treatment was done with varying concentrations of Sodium Cholate (SC) for different treatment times. These samples were then characterized using Atomic Force Microscopy (AFM) to investigate the surface properties of the samples before and after treatment. To be optimized, the graphene must remain attached to the silicon substrate. The result shows that the integrity of the graphene, which is basically the Sp2 structure, is preserved as there was no delamination from the substrate even after treatment for as long as 2 hours in 1% weight/volume concentration of the SC solution.

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Two-dimensional Epitaxial Growth of Strained InGaAs on GaAs (001)

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MRS Online Proceedings Library 2021年第1期737卷 403-408页

作者： Hong Wen Zhiming Wang G.J. Salamo MRSEC and Microelectronics-Photonics Program University of Arkansas Fayetteville USA

Molecular beam epitaxy growth of lattice mismatched In0.53Ga0.47As / GaAs(100) system is studied by in situ scanning tunneling microscope (STM) and reflection high energy electron diffraction. InGaAs layers with a thickness ranging up to 250 nm do not exhibit a smooth surface when grown under In-rich conditions. RHEED and STM confirm the well-ordered (4×2) reconstruction and mono-layer steps associated with this unique planar growth mode. Large STM scans reveal a characteristic morphology of rectangular shaped islands distributed on large flat terraces which are typically more than 300 nm width but only mono-layer steps.

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Resistive Switching in Biocompatible Glucose Films Doped With Honey for Highly Flexible Nonvolatile Memory Application

IEEE Journal on Flexible Electronics

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IEEE Journal on Flexible Electronics 2022年第4期1卷 207-213页

作者： Lee, Ke-Jing Lin, Hsin-Ni Pal, Parthasarathi Wang, Yeong-Her National Cheng-Kung University Institute of Microelectronics Department of Electrical Engineering Tainan701 Taiwan National Cheng-Kung University Program on Semiconductor Process Technology Academy of Innovative Semiconductor and Sustainable Manufacturing Tainan701 Taiwan National Sun Yat-sen University Department of Physics Kaohsiung804 Taiwan

A mixture of honey and glucose (GH) as a new natural biomaterial for resistive random access memory (RRAM) switching layer on polyethylene terephthalate (PET) substrate is presented. The flexible substrate allows the devices to be bent and used for a wider range of applications. These devices with the GH film exhibit good reproducibility and reliability over more than 300 cycles. Moreover, the ON/OFF ratio of these devices is over 105, and VSET and VRESET are lower than that of the device with a pure glucose film. The nonvolatile nature of the devices is confirmed by measuring retention for 104 s. This switching behavior is attributed to ohmic conduction and trap-controlled space charge-limited current (TC-SCLC) mechanisms that confirm filament formation and breakage at high-resistance state (HRS) and low-resistance state (LRS), respectively. © 2022 IEEE.

关键词： Sol-gel process

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An Energy-Efficient StEFCal VLSI Design with Approximate Squarer and Divider Units

An Energy-Efficient StEFCal VLSI Design with Approximate Squ...

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IEEE Latin American Symposium on Circuits and Systems (LASCAS)

作者： Morgana M. A. Da Rosa Patrícia Da Costa Guilherme Paim Eduardo Da Costa Rafael Soares Sergio Bampi Graduate Program on Computing Federal University of Pelotas (UFPel) Pelotas Brazil Graduate Program on Microelectronics Federal University of Rio Grande do Sul Porto Alegre Brazil Graduate Program on Electronic Engineering and Computing Catholic University of Pelotas Pelotas Brazil

Approximate computing attempts to maximize area and energy savings for a trade-off between quality and efficiency. This paper investigates the approximate squarer and divider units in the calibration procedure for radio astronomy called StEFCal (Statistically Efficient and Fast Calibration). The StEFCal circuit uses two squarer units from the literature, i.e., radix-4 (AxRSU) and SquASH, and iterative-based Newton-Raphson (NR) and Goldschmid (GLD) dividers. We demonstrate the efficiency of StEFCal using the approximate arithmetic operators from the Pareto-optimal that show the area- and power-quality trade-off. The results show that using the AxRSU combined with the NR divider improves the Mean Square Error (MSE) by 4.24%, with 58x more energy saving than the state-of-the-art.

关键词： Radio astronomy Circuits and systems Power quality Mean square error methods Very large scale integration Approximation algorithms Energy efficiency

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