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13th Asia-Pacific International Symposium on Electromagnetic Compatibility and Technical Exhibition, APEMC 2022

作者： Xu, Ji Wang, Da-Wei Liu, Jun Su, Guo-Dong Zhao, Wen-Sheng Xi'An Jiaotong University Key Lab of Micro-Nano Electronics and System Integration of xi'An City School of Microelectronics Shaanxi Xi'an710049 China Hangzhou Dianzi University Zhejiang Prov. Key Lab of Large-Scale Integrated Circuit Design School of Electronics Information Zhejiang Hangzhou310018 China

ISBN: (数字)9781665416719

ISBN: (纸本)9781665416719

Based on the wafer level packaging technology, different widths and lengths of the strip line was designed, fabricate and measured. Meanwhile, to characterize the high frequency characteristics of the strip line, the skin effect has been considered to the transmission line theory equivalent circuit model. The proposed model is in good agreement with the measured data of the strip line in the frequency range of 10 GHz - 110 GHz. The proposed model can effectively support the co-simulation of the active device model and passive device model in heterogeneous integrated package, accelerate the optimization speed of circuit design iteration, and help reduce the time cost of the EM simulation of layout. © 2022 IEEE.

关键词： Equivalent circuits

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Application of Vernier Principle to Photoelectric Autocollimator for Improvement of Accuracy, Angular Range and Speed 15

Application of Vernier Principle to Photoelectric Autocollim...

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15th International Scientific-Technical Conference on Actual Problems of Electronic Instrument Engineering, APEIE 2021

作者： Golitsyn, Andrey V. Golitsyn, Alexandr A. Dmitriev, Alexander K. Seyfi, Natalia A. State Technical University Design and Technology Institute of Applied MicroelectronicsLaser System Department Novosibirsk Electronic System Modeling Department Novosibirsk Russia Novosibirsk State Technical University Radiophysics Deparnment Novosibirsk State UniversityDepartment of Electrical Complexes Novosibirsk Russia Novosibirsk State Technical University Laser System Department Novosibirsk Russia Novosibirsk State Technical University Lab Quantum Cryogenic Electronics Novosibirsk Russia

ISBN: (纸本)9781665434089

An improvement of photoelectric autocollimator is proposed. Periodical structures of light source grating and photodetector array form an additional combination signal of Vernier type. The solution promises to exceed the limits of accuracy, angular range and speed imposed by finite number of photodetector elements. Calculation of a lens for trial version of the device with specified characteristics necessary to ensure measurement accuracy shows attainability of F-Theta distortion within 10-6%-tenths of nanometres, without taking manufacturing tolerances into consideration. It is significantly less than value of light spot within diffraction limit (3 microns) and typical pixel pitch of the linear or matrix sensor. The transverse aberrations also seem hard attainable lower than the diffraction limit. The processing speed of designed trial version of autocollimator is about 30 measurements per second and if needed it can be increased in case of using digital camera with higher frame rate in the device construction. © 2021 IEEE.

关键词： Light sources

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An Efficient Multi-fidelity Bayesian Optimization Approach for Analog Circuit Synthesis

arXiv

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arXiv 2019年

作者： Zhang, Shuhan Lyu, Wenlong Yang, Fan Yan, Changhao Zhou, Dian Zeng, Xuan Hu, Xiangdong State Key Lab of ASIC & System Microelectronics Department Fudan University China Shanghai High Performance Integrated Circuit Design Center China University of Texas at Dallas Dallas United States

This paper presents an efficient multi-fidelity Bayesian optimization approach for analog circuit synthesis. The proposed method can significantly reduce the overall computational cost by fusing the simple but potentially inaccurate low-fidelity model and a few accurate but expensive high-fidelity data. Gaussian Process (GP) models are employed to model the low- and high-fidelity black-box functions separately. The nonlinear map between the low-fidelity model and high-fidelity model is also modelled as a Gaussian process. A fusing GP model which combines the low- and high-fidelity models can thus be built. An acquisition function based on the fusing GP model is used to balance the exploitation and exploration. The fusing GP model is evolved gradually as new data points are selected sequentially by maximizing the acquisition function. Experimental results show that our proposed method reduces up to 65.5% of the simulation time compared with the state-of-the-art single-fidelity Bayesian optimization method, while exhibiting more stable performance and a more promising practical prospect. Copyright © 2019, The Authors. All rights reserved.

关键词： Timing circuits

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A reconfigurable routing method for fault-tolerant mesh-based network on chip

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Journal of Information and Computational Science 2013年第1期10卷 157-165页

作者： Liu, Yanhua Ruan, Ying Lai, Zongsheng Sun, Ling Institute of Microelectronics Circuit and System East China Normal University Shanghai 200241 China Jiangsu Provincial Key Lab. of ASIC Design Nantong University Nantong 226019 China State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China

As the semiconductor industry advances to nano-technology points, Network on Chip (NoC) components are becoming vulnerable to errors during the system operation. Consequently, fault-tolerant techniques for NoC are needed to achieve high reliability. In this paper, we present a fault-tolerant routing method to tolerate faulty routers in a two-dimension (2D) mesh-based NoC. With this method, the system can have a multi-router fault-tolerant capability and the routing path can be dynamically reconfigured to support different situations caused by faulty routers in NoC. Fault-tolerance capability and system performance of the proposed method are evaluated through analysis and simulations. Theoretical analysis and simulation results show that the proposed method can enhance the reliability of system and offer considerable fault-tolerance capability. © 2013 by Binary Information Press.

关键词： Network-on-chip

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Energy and thermal aware mapping for mesh-based NoC architectures using multi-objective ant colony algorithm

Energy and thermal aware mapping for mesh-based NoC architec...

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IEEE International Conference on Computer Research and Development

作者： Liu, Yanhua Ruan, Ying Lai, Zongsheng Jing, Weiping Dept. of Electronic Computer and Software Systems Institute of Microelectronics Circuit and System East China Normal University Shanghai China Dept. of Electronic Engineering Jiangsu Provincial Key Lab. of ASIC Design Nantong University Nantong China

ISBN: (纸本)9781612848372

Where IP cores to be mapped must be carefully solved for any given application in order to optimize different performance metrics in Network-on-Chip (NoC) design flow. The optimization of different performance metrics simultaneously may cause a negative effect on each other because of the strong correlation between these performance metrics. In this paper, we propose a multi-objective ant colony algorithm (MOACA) that maps IP cores onto mesh-based NoC architectures. This algorithm is an efficient way to find the pareto-optimal front which optimizes energy consumption and hotspot temperature of NoC. The algorithm has been implemented and evaluated for synthetic generated benchmarks. Experimental results confirm the efficiency, accuracy and scalability of the algorithm. © 2011 IEEE.

关键词： Network-on-chip

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Modeling and simulation for on-chip power grid networks by locally dominant krylov subspace method

Modeling and simulation for on-chip power grid networks by l...

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2008 International Conference on Computer-Aided design, ICCAD

作者： Yan, Boyuan Tan, Sheldon X.-D. Chen, Gengsheng Wu, Lifeng Department of Electrical Engineering University of California Riverside CA 92521 United States ASIC and System State-Key-Lab Microelectronics Dept. Fudan Univeristy Shanghai 200433 China Cadence Design Systems Inc. San Jose CA 95134 United States

ISBN: (纸本)9781424428205

Fast analysis of power grid networks has been a challenging problem for many years. The huge size renders circuit simulation inefficient and the large number of inputs further limits the application of existing Krylov-subspace macromodeling algorithms. However, strong locality has been observed that two nodes geometrically far have very small electrical impact on each other because of the exponential attenuation. However, no systematic approaches have been proposed to exploit such locality. In this paper, we propose a novel modeling and simulation scheme, which can automatically identify the dominant inputs for a given observed node in a power grid network. This enables us to build extremely compact models by projecting the system onto the locally dominant Krylov subspace corresponding to those dominant inputs only. The resulting simulation can be very fast with the compact models if we only need to view the responses of a few nodes under many different inputs. Experimental results show that the proposed method can have at least 100X speedup over SPICE-like simulations on a number of large power grid networks up to 1M nodes.

关键词： Circuit simulation

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An E-Nose Haar Wavelet Preprocessing Circuit for Spiking Neural Network Classification

An E-Nose Haar Wavelet Preprocessing Circuit for Spiking Neu...

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2008 IEEE International Symposium on Circuits and systems (ISCAS 2008), vol.7

作者： Jacob N. Allen Safa B. Hasan Hoda S. Abdel-Aty-Zohdy Robert L. Ewing Microelectronics System Design Lab Department of Elect. and Computer Engineering Oakland University MI USA Information Directorate Air Force Research Laboratories Wright Patterson Air Force Base OH USA

A simulation model for polymer film chemical sensors is developed based on a 1 dimensional diffusion equation. Using this model, electronic nose smell prints produced by the 32 sensor array of a Cyranose 320 are simulated to test pattern classification. A Haar wavelet filter reduces noise and captures information about the diffusion rate of the analyte in each sensor. Inputs are encoded into a binary Hamming pattern and fed into a binary spiking neural network for pattern classification. The preprocessing circuit for the spiking neural network, including the wavelet filter, is designed using standard cells for an 180nm process. Real and simulated results from the spiking neural network classification algorithm are favorably compared to Bayes, Canonical, and PCA-PNN classifiers.

关键词： Neural networks Circuit simulation Sensor arrays Chemical sensors Pattern classification Polymer films Equations Electronic noses Electronic equipment testing Circuit testing

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Modeling and simulation for on-chip power grid networks by locally dominant Krylov subspace method 08

Modeling and simulation for on-chip power grid networks by l...

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IEEE International Conference on Computer-Aided design

作者： Boyuan Yan Sheldon X.-D. Tan Gengsheng Chen Lifeng Wu Department of Electrical Engineering University of California Riverside CA USA ASIC & System State-Key-Lab MicroElectronics Department Fudan University Shanghai China Cadence Design Systems Inc. San Jose CA USA

ISBN: (纸本)9781424428205

关键词： Network-on-a-chip Power grids Power system modeling Transfer functions Attenuation Filters system-on-a-chip Application specific integrated circuits microelectronics Circuit analysis

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Wide Band Injection-Locked Quadrature Prescaler Based on Ring Oscillators

Wide Band Injection-Locked Quadrature Prescaler Based on Rin...

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2008 9th International Conference on Solid-State and Integrated-Circuit Technology

作者： Zi-yan Chen Lei Chen He-liang Ma Zong-sheng Lai Wei-ping Jing Institute of Microelectronics Circuit & System East China Normal University Engineering Research Center for Nanophotonics & Advanced Instrument Ministry of EducationEast China Normal University Nantong University Jiangsu Province Key Lab of ASIC Design

＜正＞A wide locking range injection-locked prescaler based on CMOS ring oscillators in the 0.25-μm CMOS process is ***’s free-running frequency is 1.47GHz,and the locking range covers from 1GHz to 2.4GHz with in-ph... 详细信息

关键词： Prescaler Injection-locked Technique Ring Oscillator Large Locking Range

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Bio-inspired integrated chips for telecommunications S/W defect-tracking

Bio-inspired integrated chips for telecommunications S/W def...

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ISSPIT 2007 - 2007 IEEE International Symposium on Signal Processing and Information Technology

作者： Abdel-Aty-Zohdy, Hoda S. Sherif, Mostafa Hashem Smiarowski Jr., Adam Searing, Brian Microelectronics System Design Lab. Electrical and Computer Engineering Department Oakland University Rochester MI 48309 United States Air Force Research Lab. WPAFB/RITA Dayton OH 45433-7334 United States AT and T C5-2018 Middletown NJ 007748 United States

ISBN: (纸本)9781424418350

Defect tracking is important in evaluating the reliability of the software used in telecommunication networks. Bio-inspired integrated approaches and embedded chips have been developed and implemented to track improvements in the software reliability. In this paper the integrated model for the failure discovery during testing is combined with bio-inspired approaches using the Recurrent Dynamic Neural Network (RDNN) with parametric adjustments and wavelets as basis;and the Adaptive parameters RDNN (ARDNN) where the criterion is to minimize the error in failure intensity estimation, subject to the model constraints. Simulation results favor our Adaptive Recurrent Dynamic Neural Network, with reduced error from 88% to 1.25 -to- 8% based on the number of iterations in the training phase.. The ARDNN approach provides optimum solution to the dynamic problem at hand since it iterates on the shape of the wavelet basis and provide adequate recovery of the data in the form of piecewise linear differential. ©2007 IEEE.

关键词： Piecewise linear techniques

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