检索结果-内蒙古大学图书馆

Low Temperature Co-fired Ceramic Package for lab-on-CMOS Applied in Cell Viability Monitoring

Procedia engineering 2015年 120卷 1079-1082页

作者： Niina Halonen Joni Kilpijärvi Maciej Sobocinski Timir Datta-Chaudhuri Antti Hassinen Someshekar B. Prakash Peter Möller Pamela Abshire Elisabeth Smela Sakari Kellokumpu Anita Lloyd Spetz Microelectronics and Materials Physics Laboratories Department of Electrical Engineering P.O. Box 4500 FI-90014 University of Oulu Finland Laboratory for MicroTechnologies Department of Mechanical Engineering and the Institute for Systems Research A. James Clark School of Engineering University of Maryland College Park MD 20742 USA Integrated Biomorphic Information System Laboratory Department of Electrical & Computer Engineering and the Institute for Systems Research University of Maryland College Park MD 20742 USA Faculty of Biochemistry and Molecular Medicine University of Oulu P.O. Box 5400 FI-90014 University of Oulu Finland Advanced Design Organization Intel Corporation Hillsboro USA Division of Applied Sensor Science Department of Physics Chemistry and Biology Linköping University SE-58183 Linköping Sweden

lab-on-CMOS chips (LOCMOS) are sophisticated miniaturized analysis tools based on integrated circuit (IC) microchips performing various laboratory functions. We have developed a low temperature co-fired ceramic (LTCC) package for a LOCMOS application regarding cytotoxicity assessment of nanomaterials. The LTCC packaged capacitance sensor chip is designed for long-term cell viability monitoring during nanoparticle exposure. The introduced LTCC package utilizes the flip chip bonding technique, and it is biocompatible as well as able to withstand the environmental conditions required to maintain mammalian cell culture directly on the surface of a complementary metal oxide semiconductor (CMOS) integrated circuit.

关键词： lab-on-CMOS low temperature co-fired ceramics electronics packaging cytotoxicity assesment capacitance sensing

来源：评论

学校读者我要写书评

暂无评论

Downlink Resource Allocation for a Network using Femto-Base Stations as Relays to Macro-Users

Downlink Resource Allocation for a Network using Femto-Base ...

引用

IEEE Vehicular Technology Conference

作者： Ayush Rastogi Jinhyun Park Jae Hong Lee System Design Lab Networks Division Samsung Electronics Corporation Department of Electrical and Computer Engineering INMC Seoul National University

ISBN: (纸本)9781479944811

We propose a resource allocation scheme for the downlink of a two-tier wireless network in which femto-base stations are used as relays to macro-users. In the proposed scheme, subcarriers and relays are assigned to users assuming equal power allocation by all base stations to all subcarriers, and then, power is allocated to users. Simulation results show that the proposed scheme achieves higher sum rate of users than the random subcarrier assignment (RSA) scheme, more fair resource allocation to users than the greedy scheme, and lower total transmit power of base stations than the greedy and the RSA schemes.

关键词： Downlink Femtocell Relay Resource allocation

来源：评论

学校读者我要写书评

暂无评论

Accelerating GPGPU architecture simulation

Accelerating GPGPU architecture simulation

引用

2013 ACM SIGMETRICS International Conference on Measurement and Modeling of computer systems, SIGMETRICS 2013

作者： Yu, Zhibin Eeckhout, Lieven Goswami, Nilanjan Li, Tao John, Lizy K. Jin, Hai Xu, Chengzhong Shenzhen Institute of Advanced Technology Chinese Academy of Sciences China ELIS Department Ghent University Belgium Intelligent Design of Efficient Architectures Lab. University of Florida Gainesville FL United States Department of Electrical and Computer Engineering University of Texas Austin TX United States Service Computing Technologies and System Lab./Cluster and Grid Computing Lab. HUST Wuhan China Department of Electrical and Computer Engineering Wayne State University MI United States

ISBN: (纸本)9781450319003

Recently, graphics processing units (GPUs) have opened up new opportunities for speeding up general-purpose parallel applications due to their massive computational power and up to hundreds of thousands of threads enabled by programming models such as CUDA. However, due to the serial nature of existing micro-architecture simulators, these massively parallel architectures and workloads need to be simulated sequentially. As a result, simulating GPGPU architectures with typical benchmarks and input data sets is extremely time-consuming. This paper addresses the GPGPU architecture simulation challenge by generating miniature, yet representative GPGPU kernels. We first summarize the static characteristics of an existing GPGPU kernel in a profile, and analyze its dynamic behavior using the novel concept of the divergence flow statistics graph (DFSG). We subsequently use a GPGPU kernel synthesizing framework to generate a miniature proxy of the original kernel, which can reduce simulation time significantly. The key idea is to reduce the number of simulated instructions by decreasing per-thread iteration counts of loops. Our experimental results show that our approach can accelerate GPGPU architecture simulation by a factor of 88X on average and up to 589X with an average IPC relative error of 5.6%.

关键词： Graphics processing unit

来源：评论

学校读者我要写书评

暂无评论

Accelerating GPGPU architecture simulation 13

Accelerating GPGPU architecture simulation

引用

Proceedings of the ACM SIGMETRICS/international conference on Measurement and modeling of computer systems

作者： Zhibin Yu Lieven Eeckhout Nilanjan Goswami Tao Li Lizy John Hai Jin Chengzhong Xu Shenzhen Institute of Advanced Technology Chinese Academy of Sciences Shenzhen China ELIS Department Ghent University Ghent Belgium Intelligent Design of Efficient Architectures Lab University of Florida Gainesville USA Department of Electrical and Computer Engineering University of Texas at Austin Austin USA Service Computing Technologies and System Lab/Cluster and Grid Computing Lab HUST Wuhan China Department of Electrical and Computer Engineering Wayne State University Detroit USA

ISBN: (纸本)9781450319003

关键词： micro-architecture simulation performance general purpose graphics processing unit (GPGPU)

来源：评论

学校读者我要写书评

暂无评论

Improved supervision of NN's AOA determination with limited 1-D phased-array training data

Improved supervision of NN's AOA determination with limited ...

引用

2011 IEEE National Aerospace and Electronics Conference, NAECON 2011

作者： Van Sickle, Kevin Abdel-Aty-Zohdy, Hoda S. Microelectronics and Bio-Inspired Systems Design Lab. Department of Electrical and Computer Engineering Oakland University Rochester MI United States

ISBN: (纸本)9781457710407

A sixteen-channel linear phased array radar is calibrated by means of Artificial Neural Network (ANN). Limited data are used to train the various layers of the network, for Angle of Arrival (AOA) determinacy. This is designed to increase speed of operation and to prevent over fitting. The designed simulator generates time-series data sets representing continuous span of AOA. The generated datasets are used in multilayer feedforward NNs to find the phase, which is then used as inputs to Spiking Neural Network (SNN) o determine AOA. SNNs are used for hardware implementation feasibility. The designed simulator improved the accuracy of AOA determination, and opens the door for a wide variety of radar classification applications © 2011 IEEE.

关键词： Neural networks

来源：评论

学校读者我要写书评

暂无评论

Improved supervision of NN's AOA Determination with limited 1-D Phased-Array Training Data

Improved supervision of NN's AOA Determination with limited ...

引用

IEEE National Aerospace and Electronics Conference

作者： Kevin Van Sickle Hoda S. Abdel-Aty-Zohdy Microelectronics & Bio-Inspired Systems Design Lab Department of Electrical and Computer Engineering Oakland University

ISBN: (纸本)9781457710407

A sixteen-channel linear phased array radar is calibrated by means of Artificial Neural Network (ANN). Limited data are used to train the various layers of the network, for Angle of Arrival (AOA) determinacy. This is designed to increase speed of operation and to prevent over fitting. The designed simulator generates time-series data sets representing continuous span of AOA. The generated data-sets are used in multilayer feed-forward NNs to find the phase, which is then used as inputs to Spiking Neural Network (SNN) o determine AOA. SNNs are used for hardware implementation feasibility. The designed simulator improved the accuracy of AOA determination, and opens the door for a wide variety of radar classification applications.

关键词： Simulation SNN AOA Phased Array Training-Based Limited Data Set Classification ANGLE OF ATTACK SNN gene phased array simulating hierarchical network Continuous spans

来源：评论

学校读者我要写书评

暂无评论

Hierarchically characterizing CUDA program behavior

Hierarchically characterizing CUDA program behavior

引用

IEEE International Workshop/Symposium on Workload Characterization

作者： Zhibin Yu Hai Jin Nilanjan Goswami Tao Li Lizy K. John Service Computing Technologies and System Lab/Cluster and Grid Computing Lab Huazhong University of Science and Technology Wuhan China Intelligent Design of Efficient Architecture Lab University of Florida Gainesville FL USA Department of Electrical and Computer Engineering University of Texas Austin Austin TX USA

CUDA has become a very popular programming paradigm in parallel computing area. However, very little work has been done for characterizing CUDA kernels. In this work, we measure the thread level performance, collect the basic block level characteristics, and glean the instruction level properties for about 35 programs from CUDA SDK, Parboil, and Rodinia benchmark suites. In addition, we define basic block vectors, synchronization vectors and thread similarity matrix to capture the characteristics of CUDA programs efficiently. We find that CUDA programs have some unique characteristics at each level compared to sequential programs.

关键词： Graphics processing unit Vectors Kernel Instruction sets Programming USA Councils Educational institutions

来源：评论

学校读者我要写书评

暂无评论

Addressing Response Time and Video Quality in Remote Server Based Internet Mobile Gaming

Addressing Response Time and Video Quality in Remote Server ...

引用

IEEE Conference on Wireless Communications and Networking

作者： Shaoxuan Wang Sujit Dey Mobile System Design Lab Department of Electrical and Computer Engineering University of California San Diego USA

A new remote server based gaming approach, where the responsibility of executing the gaming engines is put on remote servers instead of the mobile devices, has the potential for enabling mobile users to play the same rich Internet games available to PC users. However, the mobile gaming user experience may be limited by risks of unacceptably high response time, and low gaming video quality, as gaming control commands, and the resulting gaming video, have to travel through wireless networks characterized by high bandwidth fluctuations, latency and packet loss. In this paper, we propose a set of application layer optimization techniques to ensure acceptable gaming response time and video quality in the remote server based approach. The techniques include downlink gaming video rate adaptation, uplink delay optimization, and client play-out delay adaptation. Experiments conducted on a commercial HSDPA network demonstrate that the proposed optimization techniques can make the remote server based approach feasible, allowing rich Internet games to be played on mobile devices, while ensuring acceptable user experience.

关键词： Delay Web server Internet Games Network servers Search engines Wireless networks Bandwidth Fluctuations Downlink

来源：评论

学校读者我要写书评

暂无评论

XML defined custom microprocessors using Rapid Hardware Definition Language

XML defined custom microprocessors using Rapid Hardware Defi...

引用

IEEE National Conference on Aerospace and Electronics (NAECON)

作者： Jacob N. Allen Hoda S. Abdel-Aty-Zohdy Robert L. Ewing Microelectronics System Design Laboratory Department of Electrical and Computer Engineering Oakland University Rochester Hills MI USA Air Force Research Laboratory OH USA

Rapid HDL is an object oriented software library for scripting the generation of synthesizable Verilog. A fully functional customized microprocessor is defined and automatically synthesized for an FPGA from an XML specification file. Using a library of blocks, a microprocessor fabric is defined in XML. Control states specify the connections between the fabric blocks during microprocessor operation. Opcodes sequence the control states and provide a vocabulary for assembly programs, which are compiled and executed on the microprocessor.

关键词： Microprocessors Hardware design languages Hardware XML Registers Fabrics Software

来源：评论

学校读者我要写书评

暂无评论

A reconfigurable spiking neural network digital ASIC simulation and implementation

A reconfigurable spiking neural network digital ASIC simulat...

引用

IEEE National Conference on Aerospace and Electronics (NAECON)

作者： Kevin Van Sickle Hoda Abdel-Aty-Zohdy Microelectronics Systems Design Lab Department of Computer and Electrical Engineering Oakland University Rochester MI USA

ISBN: (纸本)9781424444946

A reconfigurable spiking neural network is implemented in a 0.5 ¿m CMOS digital tiny-chip. The connection weights are uploaded to registers on the ASIC. These weights are learned off-line, using combined simulated annealing and genetic algorithm. Large computational power and many simulations create small powerful networks that are adapted to interact with the environment. These configurations are swapped in and out of the ASIC to cope with varying situations and increase robustness. The network has been successfully tested with a simulated robot in a maze and can be extended for target recognition.

关键词： Neural networks Application specific integrated circuits Computational modeling Registers Simulated annealing Genetic algorithms computer networks Robustness Testing Robots

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：