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IEEE National Conference on Aerospace and Electronics (NAECON)

作者： Jacob N. Allen Hoda S. Abdel-Aty-Zohdy Robert L. Ewing Microelectronics System Design Laboratory Department of Electrical and Computer Engineering Oakland University Rochester Hills MI USA Air Force Research Laboratory OH USA

ISBN: (纸本)9781424444946

Powerful parallel cognitive processors can be developed by studying biologically plausible models of cognitive systems in animals and extrapolating key principles to be adapted for implementation in digital computer architectures. The network described here uses basic statistical methods such as proportion sampling on a massively parallel scale to create a general purpose pattern classifier. From these principles, we can achieve auto association and self organization that provides fundamental cognitive processing. Signal preprocessing is essential to transform the signal into a scale and rotation invariant binary pattern. The network avoids the curse of dimensionality by filtering out irrelevant inputs, allowing us to combine large sensor input vectors from multiple sources. Recent hardware designs define the network structure and state in memory, and then use accelerator processor cores to modify these memory structures in parallel.

关键词： Neural networks Neurons Biological system modeling Biology computing Biological information theory Brain modeling computer architecture microelectronics Power engineering and energy Biosensors

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Agile hardware development with rapid hardware definition language

Agile hardware development with rapid hardware definition la...

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IEEE International Conference on Electro-Information Technology

Rapid HDL is a hardware definition language developed in C# for the Microsoft .Net platform. Rapid HDL unifies digital FPGA hardware development and co-software integration. Hardware is scripted using reusable software objects, communication between hardware and software is automatic, and synthesis is automated using a free tool chain. Rapid HDL represents 18,000 lines of code and is freely available under the MIT license.

关键词： Hardware design languages Software libraries Testing Licenses microelectronics Force sensors Field programmable gate arrays Software reusability Software tools High level languages

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Modeling and simulation for on-chip power grid networks by locally dominant krylov subspace method

Modeling and simulation for on-chip power grid networks by l...

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2008 International Conference on computer-Aided design, ICCAD

作者： Yan, Boyuan Tan, Sheldon X.-D. Chen, Gengsheng Wu, Lifeng Department of Electrical Engineering University of California Riverside CA 92521 United States ASIC and System State-Key-Lab Microelectronics Dept. Fudan Univeristy Shanghai 200433 China Cadence Design Systems Inc. San Jose CA 95134 United States

ISBN: (纸本)9781424428205

Fast analysis of power grid networks has been a challenging problem for many years. The huge size renders circuit simulation inefficient and the large number of inputs further limits the application of existing Krylov-subspace macromodeling algorithms. However, strong locality has been observed that two nodes geometrically far have very small electrical impact on each other because of the exponential attenuation. However, no systematic approaches have been proposed to exploit such locality. In this paper, we propose a novel modeling and simulation scheme, which can automatically identify the dominant inputs for a given observed node in a power grid network. This enables us to build extremely compact models by projecting the system onto the locally dominant Krylov subspace corresponding to those dominant inputs only. The resulting simulation can be very fast with the compact models if we only need to view the responses of a few nodes under many different inputs. Experimental results show that the proposed method can have at least 100X speedup over SPICE-like simulations on a number of large power grid networks up to 1M nodes.

关键词： Circuit simulation

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Fractional-Order Signal Processing using a Polymer-Electrolyte Transistor

Fractional-Order Signal Processing using a Polymer-Electroly...

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51st Midwest Symposium on Circuits and systems (MWSCAS 2008), vol.2

作者： Robert L. Ewing Hoda S. Abdel-Aty-Zohdy Michael C. Hollenbeck Kenneth S. Stevens Information Directorate US Air Force Research Laboratory OH USA Microelectronics System Design Laboratory Department of Electrical and Systems Engineering Oakland University Rochester MI USA Department of Electrical and Computer Engineering University of Utah Salt Lake UT USA

Fractional-order systems have applications in the areas of Flight Control, Robotics, Missile Guidance, Control of Structural Vibrations of Space Platforms and Sensor Technology. Fractional-order transfer functions can characterize complex nonlinear dynamics with many fewer parameters than integer-order functions. This paper addresses the use of a polymer-electrolyte transistor (PET) for use in implementating fractional-order algorithms for signal processing. The PET's advantage over the conventional RC and RL circuits is that it can be both functionally scaled and varied for dynamic fractional-order parameter controllability.

关键词： Fractional-Order Signal Processing Polymer-electrolyte transistor Acid/base chemistry Diffusion Electrokinetic flow

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Modeling and simulation for on-chip power grid networks by locally dominant Krylov subspace method 08

Modeling and simulation for on-chip power grid networks by l...

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IEEE International Conference on computer-Aided design

作者： Boyuan Yan Sheldon X.-D. Tan Gengsheng Chen Lifeng Wu Department of Electrical Engineering University of California Riverside CA USA ASIC & System State-Key-Lab MicroElectronics Department Fudan University Shanghai China Cadence Design Systems Inc. San Jose CA USA

ISBN: (纸本)9781424428205

关键词： Network-on-a-chip Power grids Power system modeling Transfer functions Attenuation Filters system-on-a-chip Application specific integrated circuits microelectronics Circuit analysis

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An E-Nose Haar Wavelet Preprocessing Circuit for Spiking Neural Network Classification

An E-Nose Haar Wavelet Preprocessing Circuit for Spiking Neu...

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2008 IEEE International Symposium on Circuits and systems (ISCAS 2008), vol.7

作者： Jacob N. Allen Safa B. Hasan Hoda S. Abdel-Aty-Zohdy Robert L. Ewing Microelectronics System Design Lab Department of Elect. and Computer Engineering Oakland University MI USA Information Directorate Air Force Research Laboratories Wright Patterson Air Force Base OH USA

A simulation model for polymer film chemical sensors is developed based on a 1 dimensional diffusion equation. Using this model, electronic nose smell prints produced by the 32 sensor array of a Cyranose 320 are simulated to test pattern classification. A Haar wavelet filter reduces noise and captures information about the diffusion rate of the analyte in each sensor. Inputs are encoded into a binary Hamming pattern and fed into a binary spiking neural network for pattern classification. The preprocessing circuit for the spiking neural network, including the wavelet filter, is designed using standard cells for an 180nm process. Real and simulated results from the spiking neural network classification algorithm are favorably compared to Bayes, Canonical, and PCA-PNN classifiers.

关键词： Neural networks Circuit simulation Sensor arrays Chemical sensors Pattern classification Polymer films Equations Electronic noses Electronic equipment testing Circuit testing

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Science Letters:A robust polysilicon-assisted SCR in ESD protection application

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Journal of Zhejiang University-Science A(Applied Physics & engineering) 2007年第12期8卷 1879-1883页

作者： CUI Qiang HAN Yan DONG Shu-rong LIOU Juin-jie ESD Lab Institute of Microelectronics and Photoelectronics Zhejiang University Hangzhou 310027 China Research Center for Embedded System Zhejiang University Hangzhou 310027 China Department of Electrical and Computer Engineering University of Central Florida Orlando 32816 USA

A novel polysilicon-assisted silicon-controlled rectifier （SCR） is presented and analyzed in this paper, which is fabricated in HHNEC＇s 0.18μm EEPROM process. The polysilicon-assisted SCRs take advantage of polysilicon layer to help bypass electro-static discharge （E S D） current without occupying extra layout area. TLP current-voltage （I-V） measurement results show that given the same layout areas, robustness performance of polysilicon-assisted SCRs can be improved to 3 times of conventional MLSCR＇s. Moreover, one-finger such polysilicon-assisted SCRs, which occupy only 947 [3mz layout area, can undergo 7-kV HBM ESD stress. Results further demonstrate that the S-type I-V characteristics of polysilicon-assisted SCRs are adjustable to different operating conditions by changing the device dimensions. Compared with traditional SCRs, this new SCR can bypass more ESD currents and consumes smaller IC area.

关键词： Electro-static discharge （ESD） Silicon-controlled rectifier （SCR） Robustness performance Polysilicon-assisted Human body model （HBM）

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Biologically-Based Signal Processing Chips with Emphasis on Telecommunication Defect Tracking and Reliability Estimation

Biologically-Based Signal Processing Chips with Emphasis on ...

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IEEE Pacific Rim Conference on Communications, computers and Signal Processing

作者： Hoda S Abdel-Aty-Zohdy Microelectronics System Design Laboratory Department of Electrical and Computer Engineering Oakland University Rochester MI USA

This paper provides observations and motivations to mimic biological information processing. Alternative bio-inspired systems definitions, basics, approaches, algorithms, and chip implementations will be illustrated to offer a base of choice for bio-based Intelligent Information Processing (IIP) systems. Hybrid biological and bio-based IIP are briefly presented. Two specific applications follow with embedded bio-based systems: Bio-chemical sensing and detection E-nose; and Track improvements In the reliability of the software used in telecommunication network deployments. The biologically-based processing discoveries gleaned from observing the spikes in the brain activity of monkeys, introduced the concept of plasticity in synapses used in our embedded Spiking Neural Network (SNN) system for the E-Nose The mathematical construct of a defect tracking classifier is nonlinear, and the event to be recognized involves a sequentially varying or non-stationary phenomenon for telecommunication defect tracking and reliability estimation. Thus, Adaptive Recurrent Dynamic Neural Network (ARDNN) system using wavelet function as the basis improved the failure event estimation of software defect tracking in telecommunications and reduced the error from 88% to L25-8%.

关键词： Biomedical signal processing Signal processing algorithms Information processing Telecommunication network reliability Biological neural networks Application software Embedded software Brain Nonlinear dynamical systems Neural networks

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Bio-inspired integrated chips for telecommunications S/W defect-tracking

Bio-inspired integrated chips for telecommunications S/W def...

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ISSPIT 2007 - 2007 IEEE International Symposium on Signal Processing and Information Technology

作者： Abdel-Aty-Zohdy, Hoda S. Sherif, Mostafa Hashem Smiarowski Jr., Adam Searing, Brian Microelectronics System Design Lab. Electrical and Computer Engineering Department Oakland University Rochester MI 48309 United States Air Force Research Lab. WPAFB/RITA Dayton OH 45433-7334 United States AT and T C5-2018 Middletown NJ 007748 United States

ISBN: (纸本)9781424418350

Defect tracking is important in evaluating the reliability of the software used in telecommunication networks. Bio-inspired integrated approaches and embedded chips have been developed and implemented to track improvements in the software reliability. In this paper the integrated model for the failure discovery during testing is combined with bio-inspired approaches using the Recurrent Dynamic Neural Network (RDNN) with parametric adjustments and wavelets as basis;and the Adaptive parameters RDNN (ARDNN) where the criterion is to minimize the error in failure intensity estimation, subject to the model constraints. Simulation results favor our Adaptive Recurrent Dynamic Neural Network, with reduced error from 88% to 1.25 -to- 8% based on the number of iterations in the training phase.. The ARDNN approach provides optimum solution to the dynamic problem at hand since it iterates on the shape of the wavelet basis and provide adequate recovery of the data in the form of piecewise linear differential. ©2007 IEEE.

关键词： Piecewise linear techniques

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Bio-Inspired Integrated Chips for Telecommunications S/W Defect-Tracking

Bio-Inspired Integrated Chips for Telecommunications S/W Def...

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IEEE International Symposium on Signal Processing and Information Technology (ISSPIT)

作者： Hoda S Abdel-Aty-Zohdy Mostafa Hashem Sherif Adam Smiarowski Brian Searing WPAFB/RITA Air Force Research Laboratory OH USA Microelectronics System Design Lab Electrical and Computer Engineering Department Oakland University Rochester MI USA Middletown NJ USA

Defect tracking is important in evaluating the reliability of the software used in telecommunication networks. Bio-inspired integrated approaches and embedded chips have been developed and implemented to track improvements in the software reliability. In this paper, the integrated model for the failure discovery during testing is combined with bio-inspired approaches using the recurrent dynamic neural network (RDNN) with parametric adjustments and wavelets as basis; and the adaptive parameters RDNN (ARDNN) where the criterion is to minimize the error in failure intensity estimation, subject to the model constraints. Simulation results favor our adaptive recurrent dynamic neural network, with reduced error from 88% to 1.25 –to- 8% based on the number of iterations in the training phase.. The ARDNN approach provides optimum solution to the dynamic problem at hand since it iterates on the shape of the wavelet basis and provide adequate recovery of the data in the form of piecewise linear differential.

关键词： Software testing Neural networks Telecommunication network reliability Recurrent neural networks Genetic algorithms Parameter estimation Biomedical signal processing Information technology microelectronics computer networks

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