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37th IEEE International system-on-Chip Conference, SOCC 2024

作者： Syafalni, Infall Firdaus, Mohamad Imam Sutisna, Nana Adiono, Trio Juhana, Tutun Mulyawan, Rahmat Bandung Institute of Technology School of Electrical Engineering and Informatics Indonesia University Center of Excellence on Microelectronics Bandung Institute of Technology Indonesia The University of Tokyo System Design Laboratory School of Engineering Tokyo Japan

ISBN: (纸本)9798350377569

In this paper, we propose a novel dual-mode Q-learning hardware accelerator (DMQ) for shortest path and coverage area problems. The hardware accelerator design uses only an agent to tackle multiple modes, in this case, shortest path and coverage area problems for mobile robots. The work proposes a modified policy generator that supports two reward functions for the shortest path and coverage area. The coverage area mode has 4 × state spaces than that of the shortest path mode. We also explore some policy generators such as decreasing epsilon and greedy for the dual-mode Q-learning accelerator. Experimental results show that by using a greedy policy generator the learning rate of an agent is faster for both problems. Moreover, the hardware architecture requires only 1199 LUTs, 4 LUTRAMs, and 6 BRAMs for the dual-mode functions. With a throughput of 185.63 MHz, the proposed work outperforms other methods up to 13 × in energy efficiency. The proposed work is useful for disaster recovery, smart navigation, and other artificial intelligence applications. © 2024 IEEE.

关键词： Mobile robots

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A topological optical parametric amplifier on a CMOS-chip

A topological optical parametric amplifier on a CMOS-chip

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2023 Optica Nonlinear Optics Topical Meeting, NLO 2023

作者： Sohn, Byoung-Uk Huang, Yue-Xin Choi, Ju Won Chen, George F.R. Ng, Doris K.T. Yang, Shengyuan A. Tan, Dawn T.H. Photonics Devices and System Group Singapore University of Technology and Design Singapore487372 Singapore Research Laboratory for Quantum Materials Singapore University of Technology and Design Singapore487372 Singapore Institute of Microelectronics A*STAR 2 Fusionopolis Way #08-02 Innovis Tower Singapore138634 Singapore

ISBN: (纸本)9781957171234

We demonstrate 12.8dB optical parametric gain using a topological photonic waveguide based on the Su-Schrieffer-Heeger model with a domain wall, implemented on ultra-silicon-rich nitride. The Kerr nonlinearity is observed to induce delocalization in the topological mode. Optica Nonlinear Optics Topical Meeting 2023 © Optica Publishing Group 2023 © 2023 The Author(s)

关键词： Optical parametric amplifiers

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DMQ: Dual-Mode Q-Learning Hardware Accelerator for Shortest Path and Coverage Area

DMQ: Dual-Mode Q-Learning Hardware Accelerator for Shortest ...

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IEEE International SOC Conference

作者： Infall Syafalni Mohamad Imam Firdaus Nana Sutisna Trio Adiono Tutun Juhana Rahmat Mulyawan School of Electrical Engineering and Informatics Bandung Institute of Technology Indonesia University Center of Excellence on Microelectronics Bandung Institute of Technology Indonesia System Design Laboratory School of Engineering The University of Tokyo Tokyo Japan

ISBN: (数字)9798350377569

ISBN: (纸本)9798350377576

In this paper, we propose a novel dual-mode Q-learning hardware accelerator (DMQ) for shortest path and coverage area problems. The hardware accelerator design uses only an agent to tackle multiple modes, in this case, shortest path and coverage area problems for mobile robots. The work proposes a modified policy generator that supports two reward functions for the shortest path and coverage area. The coverage area mode has $4 \times$ state spaces than that of the shortest path mode. We also explore some policy generators such as decreasing epsilon and greedy for the dual-mode Q-learning accelerator. Experimental results show that by using a greedy policy generator the learning rate of an agent is faster for both problems. Moreover, the hardware architecture requires only 1199 LUTs, 4 LUTRAMs, and 6 BRAMs for the dual-mode functions. With a throughput of 185.63 MHz, the proposed work outperforms other methods up to $13 \times$ in energy efficiency. The proposed work is useful for disaster recovery, smart navigation, and other artificial intelligence applications.

关键词： Q-learning Navigation Disasters Throughput Generators Energy efficiency Table lookup Mobile robots Artificial intelligence Hardware acceleration

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Intra Fast Mode Decision Algorithm and Hardware design for AVS2

Intra Fast Mode Decision Algorithm and Hardware Design for A...

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2021 International Conference on Signal Processing and Machine Learning, CONF-SPML 2021

作者： Xie, Hao Liu, Kaiyang Zhao, Yang Zheng, Xiao Qing, Xianguo Nuclear Power Institute of China Science and Technology on Reactor System Design Technology Laboratory Chengdu China Peking University School of Software and Microelectronics Beijing China

ISBN: (纸本)9781665417341

AVS2 is a kind of video coding standard proposed by China, it adopts 33 intra prediction modes to improve coding performance, while the computational complexity has increased dramatically. In order to reduce the complexity of AVS2 intra mode decision and make the AVS2 hardware encoder meet real-time requirements, this paper proposes the AVS2 intra fast mode decision algorithm and hardware design. The experimental results show that the intra mode decision algorithm and hardware design proposed in this paper can meet the throughput requirement of 1920x1080@60fps at a clock frequency of 300MHz. By using Xilinx FPGA XC7K325T 900 on the Vivado HLS platform for synthesis, only 10% of the LUT, 5% of FF, 5% of BRAM, and 6% of DSP in FPGA resources are consumed to meet the design requirements. © 2021 IEEE.

关键词： Field programmable gate arrays (FPGA)

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Physical design of RISC-V based system-on-Chip using OpenLane

Physical Design of RISC-V based System-on-Chip using OpenLan...

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IEEE Asia-Pacific Conference on Circuits and systems

作者： Muhammad Fauzan Raihan Fadhil Yanuarsyah Muhammad Hanif Hibatullah Radithya Arisaputra Infall Syafalni Nana Sutisna Trio Adiono Makoto Ikeda School of Electrical Engineering and Informatics Bandung Institute of Technology Indonesia University Center of Excellence on Microelectronics Indonesia System Design Laboratory School of Engineering The University of Tokyo Tokyo Japan Graduate School of Engineering The University of Tokyo Tokyo Japan

ISBN: (数字)9798350378771

ISBN: (纸本)9798350378788

Open-source tools for designing integrated circuits are crucial for electrical engineering students. However, more references are necessary to promote the tools to the academic environments. This paper presents design and implementation of a PicoSoC (Pico system-on-Chip) using the OpenLane automated VLSI flow. The PicoSoC comprises several modules, including the PicoRV32 CPU, UART and SPI peripherals, and memory blocks. The design methodology encompasses RTL simulation, macro hardening, core hardening, full-chip hardening, and gatelevel simulation. The results indicate successful physical design and functional verification, demonstrating that the gate-level simulation outputs align with those from RTL simulation. The work is useful for designing the physical layout of digital circuits, SoC architecture development, and also promoting open-source IC design tools in academic environments.

关键词： Layout Logic gates Very large scale integration system-on-chip design tools Central Processing Unit Pins Hardware design languages Digital circuits Physical design

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design of Extended RISC-V for Q-Learning Hardware Accelerator using HW/SW Co-design

Design of Extended RISC-V for Q-Learning Hardware Accelerato...

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IEEE Asia-Pacific Conference on Circuits and systems

作者： Infall Syafalni Muhammad Sulthan Mazaya Muhammad Raihan Elfazri Eko Mursito Budi Nana Sutisna Rahmat Mulyawan Trio Adiono Makoto Ikeda School of Electrical Engineering and Informatics Bandung Institute of Technology Indonesia University Center of Excellence on Microelectronics Bandung Institute of Technology Indonesia System Design Laboratory School of Engineering The University of Tokyo Tokyo Japan Faculty of Industrial Technology Bandung Institute of Technology Indonesia Graduate School of Engineering The University of Tokyo Tokyo Japan

ISBN: (数字)9798350378771

ISBN: (纸本)9798350378788

In this paper, we propose a novel RISC-V ISA extension for a reinforcement learning-based hardware accelerator called RISC-Q. We introduce new instructions i.e., ***_constant, ***, ***, ***, and ***. Each instruction corresponds to a hardware module. The ***_constant sets necessary constants for the Q-learning by storing it in dedicated registers. The *** and *** instructions write and read the data to the main memory. The *** instruction controls the max seeker hardware module to find $\mathbf{Q}$-max values. The *** instruction accesses the $\mathbf{Q}$-updater hardware module to update the $\mathbf{Q}$-value with the corresponding state, action, and reward. Experimental result shows that the RISC-V extended reinforcement learning hardware accelerator (RISC-Q), which is implemented in the Nexys FPGA board, outperforms the software implementation up to $1.5 \times$ speed up. The work is useful for edge-computing applications such as smart navigation, smart communications, and robotics.

关键词： Q-learning Navigation Circuits and systems Asia Software Registers Hardware acceleration Robots Field programmable gate arrays

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Intra Fast Mode Decision Algorithm and Hardware design for AVS2

Intra Fast Mode Decision Algorithm and Hardware Design for A...

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2021 International Conference on Signal Processing and Machine Learning (CONF-SPML)

作者： Hao Xie Kaiyang Liu Yang Zhao Xiao Zheng Xianguo Qing Science and Technology on Reactor System Design Technology Laboratory Nuclear Power Institute of China School of Software and Microelectronics Peking University

ISBN: (纸本)9781665417358

AVS2 is a kind of video coding standard proposed by China,it adopts 33 intra prediction modes to improve coding performance,while the computational complexity has increased *** order to reduce the complexity of AVS2 intra mode decision and make the AVS2 hardware encoder meet realtime requirements,this paper proposes the AVS2 intra fast mode decision algorithm and hardware *** experimental results show that the intra mode decision algorithm and hardware design proposed in this paper can meet the throughput requirement of 1920 x1080@60 fps at a clock frequency of300 *** using Xilinx FPGA XC7 K325 T 900 on the Vivado HLS platform for synthesis,only 10% of the LUT,5% of FF,5% of BRAM,and 6% of DSP in FPGA resources are consumed to meet the design requirements.

关键词： AVS2 intra coding mode decision

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High spectro-temporal compression on a nonlinear CMOS-chip

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Light(Science & Applications) 2021年第7期10卷 1347-1361页

作者： Ju Won Choi Ezgi Sahin Byoung-Uk Sohn George F.R.Chen Doris K.T.Ng Anuradha M.Agarwal Lionel C.Kimerling Dawn T.H.Tan Photonics Devices and System Group SUTD-MIT International Design CenterSingapore University of Technology and DesignSingapore 487372Singapore Institute of Microelectronics A*STAR(Agency for ScienceTechnology and Research)2 Fusionopolis Way#08-02Innovis TowerSingapore 138634Singapore Microphotonics Center Massachusetts Institute of Technology77 Massachusetts AvenueCambridgeMA 02139USA Materials Research Laboratory Massachusetts Institute of Technology77 Massachusetts AvenueCambridgeMA 02139USA Department of Materials Science and Engineering Massachusetts Institute of Technology77 Massachusetts AvenueCambridgeMA 02139USA

Optical pulses are fundamentally defined by their temporal and spectral *** ability to control pulse properties allows practitioners to efficiently leverage them for advanced metrology,high speed optical communications and attosecond ***,we report 11×temporal compression of 5.8 ps pulses to 0.55 ps using a low power of 13.3 *** result is accompanied by a significant increase in the pulse peak power by 9.4×.These results represent the strongest temporal compression demonstrated to date on a complementary metal–oxide–semiconductor(CMOS)*** addition,we report the first demonstration of on-chip spectral compression,3.0×spectral compression of 480 fs pulses,importantly while preserving the pulse *** strong compression achieved at low powers harnesses advanced on-chip device design,and the strong nonlinear properties of backend-CMOS compatible ultra-silicon-rich nitride,which possesses absence of two-photon absorption and 500×larger nonlinear parameter than in stoichiometric silicon nitride *** demonstrated work introduces an important new paradigm for spectro-temporal compression of optical pulses toward turn-key,on-chip integrated systems for all-optical pulse control.

关键词： pulse optical nonlinear

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The Effect of Device Redundancy in Timeliness of Information

The Effect of Device Redundancy in Timeliness of Information

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IEEE International Conference on Communications (ICC)

作者： Kang Lang Zhengchuan Chen Nikolaos Pappas Howard H. Yang Yunjian Jia Tony Q. S. Quek School of Microelectronics and Communication Engineering Chongqing University Chongqing China State Key Laboratory of Integrated Services Networks Xidian University Xi'an China Department of Computer and Information Science Linköping University Linköping Sweden Zhejiang University/University of Illinois at Urbana-Champaign Institute Zhejiang University Haining China Information System Technology and Design Pillar Singapore University of Technology and Design Singapore

Emerging interaction-based Internet of Things (IoT) applications have stringent demand for timeliness, imposing critical challenges to the design of status update system. Using redundant devices to update the status of the same process is a promising way to improve timeliness, but this approach can result in out of order update arrivals, making it difficult to analyze timeliness. To that end, the present paper conducts a theoretical study toward the Age of Information (AoI) of a multi-queue status update system where multiple sensors observe one physical process and update a common monitor. Based on the stochastic hybrid systems method, the average AoI of the considered system is derived in closed form. The theoretical results are consistent with the simulation results, verifying the correctness of the theoretical analysis. It is shown that the logarithm of the average AoI is linearly decreasing with the logarithm of the number of sensors.

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Enhancing energy efficiency in shipping container house: A novel approach using hybrid louver systems

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Energy and Built Environment 2024年

作者： Ibrahim, Adnan Alsukkar, Muna Dong, Yifang Saleem, Farrukh Hamza, Amir Hu, Peng Hu, MaoBin Department of Thermal Science and Energy Engineering University of Science and Technology of China Hefei230027 China Department of Architectural Engineering Faculty of Engineering The Hashemite University P.O. Box 330127 Zarqa13133 Jordan Institute of Microelectronics Chinese Academy of Sciences Beijing100029 China CAS Key Laboratory of Mechanical Behavior and Design of Materials Department of Modern Mechanics CAS Center for Excellence in Complex System Mechanics University of Science and Technology of China Hefei China School of Engineering Science University of Science and Technology of China Hefei230026 China

Reusing shipping containers for residential purposes offers a promising approach to address global energy consumption challenges from economic and environmental perspectives. This study parametrically designed hybrid louver shadings by combining fixed vertical triangular slats with variable-depth horizontal rectangular slats, offering a novel approach to shading prefabricated buildings. The energy consumption, daylighting performance, and visual comfort were assessed for various shading configurations. Results indicated that implementing the proposed hybrid louvers, featuring fixed vertical triangular slats and variable-depth horizontal rectangular slats, significantly reduced Energy Use Intensity (EUI) to 133.95 kWh/m2. Moreover, Useful daylight illuminance (UDI), Daylight Autonomy (DA), and Glare Autonomy (GA) values improved to 95.38%, 89.97%, and 91.16%, respectively. The study highlighted the potential of the proposed shading system to significantly reduce overall energy consumption across various ASHRAE climate zones, including Miami (1A), Guangzhou (2A), Melbourne (3C), Esperance (3C), San Diego (3A), and Milan (4A). Notably, energy reductions of up to 50.2% were projected for climates such as Miami (1A) and San Diego (3A). Furthermore, container buildings in warm climate zones exhibited a significantly lower EUI range of 76.58 to 91.95 kWh/m². This study underscores the transformative potential of hybrid louver systems in promoting the widespread adoption of sustainable residential architecture, contributing to global sustainability efforts. © 2024 Southwest Jiatong University

关键词： Daylighting

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