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High spectro-temporal compression on a nonlinear CMOS-chip

Light(Science & Applications) 2021年第7期10卷 1347-1361页

作者： Ju Won Choi Ezgi Sahin Byoung-Uk Sohn George F.R.Chen Doris K.T.Ng Anuradha M.Agarwal Lionel C.Kimerling Dawn T.H.Tan Photonics Devices and System Group SUTD-MIT International Design CenterSingapore University of Technology and DesignSingapore 487372Singapore Institute of Microelectronics A*STAR(Agency for ScienceTechnology and Research)2 Fusionopolis Way#08-02Innovis TowerSingapore 138634Singapore Microphotonics Center Massachusetts Institute of Technology77 Massachusetts AvenueCambridgeMA 02139USA Materials Research Laboratory Massachusetts Institute of Technology77 Massachusetts AvenueCambridgeMA 02139USA Department of Materials Science and Engineering Massachusetts Institute of Technology77 Massachusetts AvenueCambridgeMA 02139USA

Optical pulses are fundamentally defined by their temporal and spectral *** ability to control pulse properties allows practitioners to efficiently leverage them for advanced metrology,high speed optical communications and attosecond ***,we report 11×temporal compression of 5.8 ps pulses to 0.55 ps using a low power of 13.3 *** result is accompanied by a significant increase in the pulse peak power by 9.4×.These results represent the strongest temporal compression demonstrated to date on a complementary metal–oxide–semiconductor(CMOS)*** addition,we report the first demonstration of on-chip spectral compression,3.0×spectral compression of 480 fs pulses,importantly while preserving the pulse *** strong compression achieved at low powers harnesses advanced on-chip device design,and the strong nonlinear properties of backend-CMOS compatible ultra-silicon-rich nitride,which possesses absence of two-photon absorption and 500×larger nonlinear parameter than in stoichiometric silicon nitride *** demonstrated work introduces an important new paradigm for spectro-temporal compression of optical pulses toward turn-key,on-chip integrated systems for all-optical pulse control.

关键词： pulse optical nonlinear

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A silver-graphene modified acetylcholinesterase biosensor for detecting organophosphate pesticides

A silver-graphene modified acetylcholinesterase biosensor fo...

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International Conference on (ICEPT) Electronic Packaging Technology

作者： Wangbo Wangbo Wenha Shu Huaying Hu Jianhua Zhang Lianqiao Yang Microelectronics research&design center Shanghai University Key Laboratory of Advanced Display and System Applications Ministry of Education Shanghai China

ISBN: (数字)9781728150642

ISBN: (纸本)9781728150659

A highly sensitive, stable electrochemical acetylcholinesterase biosensor with silver-graphene modified was fabricated to detect organophosphorus pesticides, dichlorvos. Complete production and test process were characterized by scanning electron microscopy, cyclic voltammetry, differential pulse voltammetry. The electrochemical signal of biosensor got to be well amplified because of the modification of silver-graphene. The better detection performance was got, compared with the sensors that lack or no modified. Moreover, TiO2 sol-gel and high viscous chitosan were used as a highly efficient immobilization matrix for immobilizing acetylcholinesterase. The detection linear range of the biosensor to dichlorvos, a model organophosphorus pesticides compound, was from 0.036 μM (7.9 ppb) to 22.6 μM, with a limit of detection of 7.4 nM (1.6 ppb). The biosensor was highly reproducible and stable in detection and storage.

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Agile hardware development with rapid hardware definition language

Agile hardware development with rapid hardware definition la...

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IEEE International Conference on Electro-Information Technology

作者： Jacob N. Allen Hoda S. Abdel-Aty-Zohdy Robert L. Ewing Microelectronics System Design Laboratory Department of Electrical and Computer Engineering Oakland University Rochester Hills MI USA Air Force Research Laboratory OH USA

Rapid HDL is a hardware definition language developed in C# for the Microsoft .Net platform. Rapid HDL unifies digital FPGA hardware development and co-software integration. Hardware is scripted using reusable software objects, communication between hardware and software is automatic, and synthesis is automated using a free tool chain. Rapid HDL represents 18,000 lines of code and is freely available under the MIT license.

关键词： Hardware design languages Software libraries Testing Licenses microelectronics Force sensors Field programmable gate arrays Software reusability Software tools High level languages

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Cognitive processing using spiking neural networks

Cognitive processing using spiking neural networks

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IEEE National Conference on Aerospace and Electronics (NAECON)

ISBN: (纸本)9781424444946

Powerful parallel cognitive processors can be developed by studying biologically plausible models of cognitive systems in animals and extrapolating key principles to be adapted for implementation in digital computer architectures. The network described here uses basic statistical methods such as proportion sampling on a massively parallel scale to create a general purpose pattern classifier. From these principles, we can achieve auto association and self organization that provides fundamental cognitive processing. Signal preprocessing is essential to transform the signal into a scale and rotation invariant binary pattern. The network avoids the curse of dimensionality by filtering out irrelevant inputs, allowing us to combine large sensor input vectors from multiple sources. Recent hardware designs define the network structure and state in memory, and then use accelerator processor cores to modify these memory structures in parallel.

关键词： Neural networks Neurons Biological system modeling Biology computing Biological information theory Brain modeling Computer architecture microelectronics Power engineering and energy Biosensors

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XML defined custom microprocessors using Rapid Hardware Definition Language

XML defined custom microprocessors using Rapid Hardware Defi...

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IEEE National Conference on Aerospace and Electronics (NAECON)

Rapid HDL is an object oriented software library for scripting the generation of synthesizable Verilog. A fully functional customized microprocessor is defined and automatically synthesized for an FPGA from an XML specification file. Using a library of blocks, a microprocessor fabric is defined in XML. Control states specify the connections between the fabric blocks during microprocessor operation. Opcodes sequence the control states and provide a vocabulary for assembly programs, which are compiled and executed on the microprocessor.

关键词： Microprocessors Hardware design languages Hardware XML Registers Fabrics Software

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Optimal-weights sensors-measurement fusion using genetic algorithms

Optimal-weights sensors-measurement fusion using genetic alg...

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Midwest Symposium on Circuits and systems (MWSCAS)

作者： M.S. Sharawi H.S. Abdel-Aty-Zohdy R.L. Ewing Microelectronics System Design Laboratory Electrical and Systems Engineering Oakland University Rochester MI USA US Air Force Research Laboratory Dayton OH USA

ISBN: (纸本)078037150X

Although there are many simulated Genetic Algorithms (GAs) in applications, less research has been directed toward their practical hardware implementations. In this paper we present a GA for optimum sensors-measurement fusion and characteristic weights. A multilevel verification of the GA is performed via the Mentor Graphics design Architect (DA) and ModelSim CAD tools. In particular the design of efficient universal multipliers, dividers, and their integrated circuits is addressed. Effective mutation and crossover approach has been implemented in the GA system operation. It requires 960 clock cycles for complete iteration of 64 chromosomes, each with 3 genes of two binary-bits. This requires only 12 /spl mu/sec when implemented in the 0.25 /spl mu/m CMOS technology. The GA system is developed for a preprocessing unit to select optimal weights from real-time sensors measurement, and for fused measurements as in an electronic nose, integrated accelerometer systems, and for performance enhancement of recurrent dynamic neural networks in noisy environments. The proposed approach, simulation results, and possible experimental results are presented.

关键词： Genetic algorithms CMOS technology Hardware Graphics design automation Genetic mutations Clocks Biological cells Integrated circuit technology Real time systems

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ANN digitally programmable analog synapse

ANN digitally programmable analog synapse

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Midwest Symposium on Circuits and systems (MWSCAS)

作者： M. Al-Nsour H. Abdel-Aty-Zhody Microelectronics System Design Laboratory Department of Electrical and Systems Engineering Oakland University Rochester MI USA Oakland University Rochester MI US

An Artificial Neural Network (ANN) synapse with local digital weight storage capability is presented. It utilizes a novel, compact, voltage mode multiplying digital-to-analog converter to perform multiplication between an analog input and a digital weight. A 6-bit signed weight synapse chip has been implemented in VLSI through MOSIS 1.2 micrometer n-well CMOS technology. It occupies a total area of 1.35 mm/sup 2/. With +3 Volts supply, the circuit accepts analog inputs within /spl plusmn/1 V. Output is also within /spl plusmn/1 V. Maximum power consumption is 20 mW and total error is less than 3%. Circuit analysis and performance evaluation is presented.

关键词： Voltage Circuits Artificial neural networks Digital-analog conversion CMOS technology Energy consumption Silicon Capacitance microelectronics Laboratories

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A dual 3-V 32-MS/s CMOS switched-current ADC for telecommunication applications

A dual 3-V 32-MS/s CMOS switched-current ADC for telecommuni...

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IEEE International Symposium on Circuits and systems (ISCAS)

作者： B.E. Jonsson H. Tenhunen Microelectronics Ericsson Radio Systems AB Stockholm Sweden Electronic System Design Laboratory ETH-Electrum Royal Institute of Technology Stockholm Sweden

The potential for switched-current A/D converters in low-voltage, telecommunication applications with a high level of integration is investigated through a test design. A dual, 3 V, 32 MS/s A/D converter was fabricated in a standard digital 5 V, 0.8 /spl mu/m CMOS process. Fully differential first-generation switched-current circuits with common-mode feedforward are used to implement a 1.5-b/stage pipelined ADC core. Eight time-interleaved ADC cores operating at 4 MS/s are used to achieve a high sample rate. With channel compensation, the measured SFDR is more than 50 dB at 32 MS/s with f/sub in/=1.13 MHz. The ADC-core was measured to have 60.3 dB peak SFDR, 46.5 dB peak SNDR, and approximately 20 MHz input bandwidth. The resolution of the parallel ADC was limited by additional noise and the useful bandwidth was lowered by a fixed-pattern timing error that could not be removed by channel calibration.

关键词： Telecommunication switching Calibration CMOS technology Frequency estimation Circuits Timing Wideband Mirrors CMOS process Bandwidth

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Exploring the biocomputing frontier

Exploring the biocomputing frontier

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Midwest Symposium on Circuits and systems (MWSCAS)

作者： R.L. Ewing H.S. Abdel-Aty-Zohdy L. Liou J.B. Moncrief Information Directorate US Air Force Research Laboratory OH USA Microelectronics System Design Laboratory Department of Electrical and Systems Engineering Oakland University Rochester MI USA

Stop thinking that the universe is best described by Boolean order operations, consider the world of biocomputing. The idea in exploring the multidimensional characteristics of biocomputing systems involves multilevel protein logic interaction with hybrid digital systems (bio/digital/analog systems). In the protein biocomputing world, all models are multilevel and nonlinear exponential in nature. These biocomputing systems are linearized by boundary limited frequency, time response and dimensional ranges. The protein model and its correct development is probably the most difficult aspect for biocomputing issues. Previous protein models were not dealing with 2 and 3 dimensional models, while the current protein models are now faced with high frequency design, due to the emergence of bio-nanodevices. These future biocomputing devices will be chemical sensors, fluidic computer systems, optical switches, nanoactuators, self-repairing polymorphic computing systems, cognitive processors and biorobotics

关键词： Frequency Optical computing Multidimensional systems Logic Digital systems Time factors Protein engineering Chemical sensors Optical switches Nanoscale devices

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Plastic NNs for biochemical detection

Plastic NNs for biochemical detection

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IEEE International Symposium on Circuits and systems (ISCAS)

作者： H.S. Abdel-Aty-Zohdy J.N. Allen R.L. Ewing Microelectronics System Design Laboratory Oakland University Rochester MI USA Air Force Research Laboratory Information Directorate Wright Patterson Air Force Base OH USA

Bio-inspired systems including neural networks (NNs) have proven to be a useful tool for biochemical electronic nose. Silicon embedded olfactory pattern recognition systems however, have been limited in scale due to inherent constraints of synapse routing and chip area. This paper presents a new plastic-based NN approach for a pseudo bloodhound nose for odorant learning and detection. The network uses spike driven plastic synapses, and is designed to accept more than 1000 inputs and detect odors via an unlimited number of outputs. The basic theory is presented, including stochastic learning and detection based on hamming distance. Simulation shows the network functions well, even in noisy environments where more than 10% of inputs are contaminated by background noise. Digital hardware implementation using VHDL shows that a representative system with 128 inputs and 8 outputs fits on a single Xilinx Virtex v1000 chip and would occupy just 0.118 mm/sup 2/ using 0.16/spl mu/m CMOS technology.

关键词： Plastics Neural networks Background noise CMOS technology Electronic noses Silicon Olfactory Pattern recognition Routing Stochastic resonance

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