system-on-Chip solid state circuits that sense, receive, transmit, and process signals are the sensors, or eyes and ears, of the medical field of the millennium. The goal and design of the system-on-Chip (SOC) program...
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ISBN:
(纸本)078037150X
system-on-Chip solid state circuits that sense, receive, transmit, and process signals are the sensors, or eyes and ears, of the medical field of the millennium. The goal and design of the system-on-Chip (SOC) program for industry will be to provide affordable, reproducible, and reliable front-end instrumentation, components and subsystems for medical systems. To process/store/analyze the signals acquired from these medical sensors, analog/digital systems are used to provide data fusion and information extraction. These biomedical smart sensors cover the hybrid domains of mixed-technology (electrical, mechanical, optical, thermal, biochemical) and mixed-concept (electrical, control, digital signal processing). These significant domain design differences impose robust design challenges for medical sensor technology.
An improved design of a dynamic flip-flop is presented. The proposed design overcomes the problem of the glitch at the output and improves power-delay product for about 27%, while preserving logic embedding property. ...
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An improved design of a dynamic flip-flop is presented. The proposed design overcomes the problem of the glitch at the output and improves power-delay product for about 27%, while preserving logic embedding property. This is accomplished by equalizing the t/sub pLH/ and t/sub pHL/ of the flip-flop and careful design of keeper elements in the circuit. New design introduces insignificant area increase.
An improved design of a hybrid latch flip-flop is presented. The proposed design overcomes the problem of the glitch at the output and reduces the power consumption and delay of the circuit resulting in a total power-...
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An improved design of a hybrid latch flip-flop is presented. The proposed design overcomes the problem of the glitch at the output and reduces the power consumption and delay of the circuit resulting in a total power-delay-product improvement of about 20%. It also exhibits better soft-clock edge properties compared to the original circuit. This is accomplished by careful design of keeper elements and introducing the feedback path to suppress unnecessary transitions in the circuit. The new design introduces an insignificant area increase.
Interconnect delay is dominant in today's high speed VLSI circuits and there have been various studies on ways to resolve it. A repeater insertion tool "RePertory" has been developed to solve the interco...
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Interconnect delay is dominant in today's high speed VLSI circuits and there have been various studies on ways to resolve it. A repeater insertion tool "RePertory" has been developed to solve the interconnect timing problem on a 300 MHz 128-bit 2-way superscalar microprocessor. Because of its practical simple algorithm, the location of over 5700 repeaters distributed over 5 modules is calculated in 26 minutes on 5 UltraSPARC-II 360 MHz in parallel. This paper describes the goals of RePertory for this project, the timing improvement flow with RePertory, the results and analysis of this repeater insertion method.
High performance NMOS analog circuits which perform voltage addition, average weighing, and signal scaling are presented. Utilization of these circuits in artificial neural network applications is briefly discussed. T...
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High performance NMOS analog circuits which perform voltage addition, average weighing, and signal scaling are presented. Utilization of these circuits in artificial neural network applications is briefly discussed. The circuits are characterized by a simple structure which offers compactness, low voltage supply, and wide input range. In addition, inputs and outputs are voltages which eliminate the need for current voltage conversion. Hence, reduced power consumption and higher performance is achieved. A two-input analog adder has been accomplished through MOSIS 2.0 /spl mu/m n-well CMOS technology at Orbit Semiconductors, and occupies an area of 135/spl times/145 /spl mu/m/sup 2/. Inputs are within /spl plusmn/3 V for 3.3 V supply. Power consumption is less than 0.5 mW and THD is less than -36 dB. Measurements and performance evaluation are presented.
This paper approaches electronic nose design from two promising angles: reinforcement neural network (RNN) learning algorithms, and naturally compatible analog circuits. This approach is inspired by biological sensing...
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This paper approaches electronic nose design from two promising angles: reinforcement neural network (RNN) learning algorithms, and naturally compatible analog circuits. This approach is inspired by biological sensing and discrimination of a multitude of odors in a background environment. A VLSI system approach is presented for classification of chemical compounds, with knowledge of key features only. Based on utilizing microsensor arrays, reinforcement neural networks are used to affect nonparametric pattern recognition, classification, and distinction among multicomponent chemicals. A specialized RNN approach is chosen. Realization and implementation of analog RNN circuits is presented using 1.2 /spl mu/m CMOS n-well technology, at AMI, through the MOSIS facilities. Preliminary results are satisfactory and lend evidence to the effectiveness of the analog designed neural network building blocks for temporal and spatial NN pattern recognition.
An Artificial Neural Network (ANN) synapse with local digital weight storage capability is presented. It utilizes a novel, compact, voltage mode multiplying digital-to-analog converter to perform multiplication betwee...
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An Artificial Neural Network (ANN) synapse with local digital weight storage capability is presented. It utilizes a novel, compact, voltage mode multiplying digital-to-analog converter to perform multiplication between an analog input and a digital weight. A 6-bit signed weight synapse chip has been implemented in VLSI through MOSIS 1.2 micrometer n-well CMOS technology. It occupies a total area of 1.35 mm/sup 2/. With +3 Volts supply, the circuit accepts analog inputs within /spl plusmn/1 V. Output is also within /spl plusmn/1 V. Maximum power consumption is 20 mW and total error is less than 3%. Circuit analysis and performance evaluation is presented.
We describe direct extraction techniques for the most important parameters of a new physics-based polysilicon (poly-Si) TFT model, suitable for circuit simulation. The physics-based model covers all operating regimes ...
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We describe direct extraction techniques for the most important parameters of a new physics-based polysilicon (poly-Si) TFT model, suitable for circuit simulation. The physics-based model covers all operating regimes using continuous functions, includes short-channel effects and has been validated for devices of channel lengths down to 2 /spl mu/m. In spite of a small parameter set, the model includes the necessary dependencies on channel length.
A proof of correctness of a given VLSIC systemdesign is established by proving the consistency and implication of the implemented design with respect to the specified design. The set of conditions that establish such...
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