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arXiv 2023年

作者： Shu, Yuhao Zhang, Hongtu Sun, Hao Zhang, Mengru Zhao, Wenfeng Deng, Qi Tang, Zhidong Yuan, Yumeng Hu, Yongqi Gu, Yu Kou, Xufeng Ha, Yajun School of Information Science and Technology ShanghaiTech University Shanghai China Shanghai Institute of Microsystem and Information Technology Chinese Academy of Sciences Shanghai China School of Electronic Electrical and Communication Engineering University of Chinese Academy of Sciences Beijing China State Key Laboratory of Integrated Chip and System Frontier Institute of Chip and System Fudan University Shanghai China State Key Laboratory of ASIC and System School of Microelectronics Fudan University Shanghai China Department of Electrical and Computer Engineering Binghamton University SUNY BinghamtonNY United States Shanghai Advanced Research Institute Chinese Academy of Sciences Shanghai China Shanghai Engineering Research Center of Energy Efficient and Custom AI IC Shanghai China

Compute-in-memory (CIM) presents an attractive approach for energy-efficient computing in data-intensive applications. However, the development of suitable memory designs to achieve high-performance CIM remains a challenging task. Here, we propose a cryogenic quasi-static embedded DRAM to address the logic-memory mismatch of CIM. Guided by the re-calibrated cryogenic device model, the designed four-transistor bit-cell achieves full-swing data storage, low power consumption, and extended retention time at cryogenic temperatures. Combined with the adoption of cryogenic write bitline biasing technique and readout circuitry optimization, our 4Kb cryogenic eDRAM chip demonstrates a 1.37×106 times improvement in retention time, while achieving a 75 times improvement in retention variability, compared to room-temperature operation. Moreover, it also achieves outstanding power performance with a retention power of 112 fW and a dynamic power of 108 µW at 4.2 K, which can be further decreased by 7.1% and 13.6% using the dynamic voltage scaling technique. This work reveals the great potential of cryogenic CMOS for high-density data storage and lays a solid foundation for energy-efficient CIM implementations. Copyright © 2023, The Authors. All rights reserved.

关键词： Computation theory

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Hybrid memristor-CMOS neurons for in-situ learning in fully hardware memristive spiking neural networks

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Science Bulletin 2021年第16期66卷 1624-1633,M0003页

作者： Xumeng Zhang Jian Lu Zhongrui Wang Rui Wang Jinsong Wei Tuo Shi Chunmeng Dou Zuheng Wu Jiaxue Zhu Dashan Shang Guozhong Xing Mansun Chan Qi Liu Ming Liu Frontier Institute of Chip and System Fudan UniversityShanghai 200433China Key Laboratory of Microelectronic Devices&Integrated Technology Institute of MicroelectronicsChinese Academy of SciencesBeijing 100029China University of Chinese Academy of Sciences Beijing 100049China Department of Electrical and Electronic Engineering the University of Hong KongHong KongChina Zhejiang Laboratory Hangzhou 311122China Department of Electronic and Computer Engineering the Hong Kong University of Science and TechnologyHong KongChina

Spiking neural network,inspired by the human brain,consisting of spiking neurons and plastic synapses,is a promising solution for highly efficient data processing in neuromorphic ***,memristor-based neurons and synapses are becoming intriguing candidates to build spiking neural networks in hardware,owing to the close resemblance between their device dynamics and the biological ***,the functionalities of memristor-based neurons are currently very limited,and a hardware demonstration of fully memristor-based spiking neural networks supporting in-situ learning is very ***,a hybrid spiking neuron combining a memristor with simple digital circuits is designed and implemented in hardware to enhance neuron *** hybrid neuron with memristive dynamics not only realizes the basic leaky integrate-and-fire neuron function but also enables the in-situ tuning of the connected synaptic ***,a fully hardware spiking neural network with the hybrid neurons and memristive synapses is experimentally demonstrated for the first time,and in-situ Hebbian learning is achieved with this *** work opens up a way towards the implementation of spiking neurons,supporting in-situ learning for future neuromorphic computing systems.

关键词： Memristor Hybrid neuron In-situ learning Fully hardware Spiking neural network

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SI-YOLO: A Deep Learning Algorithm Suitable for Surgical Instrument Detection

SSRN

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SSRN 2022年

作者： Liu, Zhenzhong Zhou, Yifan Sun, Qiyuan Wang, Yan Polat, Kemal Nour, Majid Alenezi, Fayadh Alhudhaif, Adi Tianjin Key Laboratory for Advanced Mechatronic System Design and Intelligent Control School of Mechanical Engineering Tianjin University of Technology Tianjin300384 China Tianjin300384 China Department of Electrical and Electronics Engineering Bolu Abant Izzet Baysal University Bolu14280 Turkey Department of Electrical and Computer Engineering Faculty of Engineering King Abdulaziz University Jeddah21589 Saudi Arabia Department of Electrical Engineering College of Engineering Jouf University 72238 Saudi Arabia Department of Computer Science College of Computer Engineering and Sciences in Al-kharj Prince Sattam bin Abdulaziz University P.O. Box 151 Al-Kharj 11942 Saudi Arabia

Surgical instrument detection and tracking is one of the core technologies of surgical robots, which can assist clinicians in completing operations. However, existing methods need further improvement in terms of real-time performance and accuracy. We propose a deep learning algorithm, SI-YOLO, for detection of surgical instruments. SimAM attention mechanism is used to improve the feature extraction ability of YOLOv5. Replacing PANet with BiFPN in the neck network improves the feature fusion strategy. The α-IoU loss function is used to improve the regression accuracy of detection boxes. The mAP and FPS of the SI-YOLO reach 99.2% and 120 frames/sec, respectively. Aiming at the problem of ID transformation in the disappearance and occlusion of surgical instruments, the Inception-ResNet-v2 structure is added on the basis of the appearance feature extraction network Cosine of the DeepSort tracking algorithm. Combining SI-YOLO with the improved DeepSort implements the Tracking by Detection (TBD) algorithm. In the case of device disappearance or occlusion, the frequency of ID transitions is reduced by approximately 30%. Finally, we built a simulated surgery experimental platform, established our own data set, and realized the preliminary application of the proposed algorithm. © 2022, The Authors. All rights reserved.

关键词： Object detection

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Disjoint-Path and Golden-Pin Based Irregular PCB Routing with Complex Constraints

Disjoint-Path and Golden-Pin Based Irregular PCB Routing wit...

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design Automation Conference

作者： Qinghai Liu Qinfei Tang Jiarui Chen Chuandong Chen Ziran Zhu Huan He Jianli Chen Yao-Wen Chang Center for Discrete Mathematics Fuzhou University Fuzhou China Fujian Science & Technology Innovation Laboratory for Optoelectronic Information of China Fuzhou China College of Computer and Date Science Fuzhou University Fuzhou China Department of Microelectronics Fuzhou University Fuzhou China Department of Microelectronics Southeast University Nanjing China Hangzhou Huawei Enterprises Telecommunication Technologies Co. Ltd Hangzhou China State Key Lab of ASIC & System Fudan University Shanghai China Graduate Institute of Electronics Engineering National Taiwan University Taipei Taiwan Department of Electrical Engineering National Taiwan University Taipei Taiwan

PCB routing becomes time-consuming as the complexity of PCB design increases. Unlike traditional schemes that treat the two essential PCB routing processes separately, namely, escape and bus routing, we consider the continuity between them and present a golden-pin-based routing scheme to find the desired solution with angle and topology constraints. Further, conventional rip-up and reroute methods are often ineffective and inefficient for congestion alleviation and routability optimization. We construct a component graph by modeling components as vertices and applying the minimum weight vertex covering method to improve the routability. A self-adaptable ordering method is presented for escape routing to arrange the pin order on the component boundary, guaranteeing successful bus routing. In addition, escape routing is performed based on a disjoint path method. We construct a dynamic Hanan grid in bus routing and utilize a novel congestion adjustment technique to improve solution quality. Compared with FreeRouting and Allegro, the experiment results show that our algorithm achieves high routability and a significant 90% runtime reduction.

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Information Freshness in A Dual Monitoring system

Information Freshness in A Dual Monitoring System

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GLOBECOM 2022 - 2022 IEEE Global Communications Conference

作者： Dapeng Deng Zhengchuan Chen Howard H. Yang Nikolaos Pappas Limei Hu Min Wang Yunjian Jia Tony Q.S. Quek School of Microelectronics and Communication Engineering Chongqing University Chongqing China National Mobile Communications Research Laboratory Southeast University Nanjing China Zhejiang University/University of Illinois at Urbana-Champaign Institute Zhejiang University Haining China Department of Computer and Information Science Linkoping University Linkoping Sweden School of Optoelectronics Engineering Chongqing University of Posts and Telecommunications Chongqing China Information System Technology and Design Pillar Singapore University of Technology and Design Singapore

ISBN: (纸本)9781665435413

We study the average age of information (AoI) and peak AoI (PAoI) of a dual-queue status update system that monitors a common stochastic process. We capture the state transition characteristics of the considered system by establishing a Markov chain. Using the state flow graph analysis method, we derive closed-form expressions of the average peak age of information (PAoI) and the average age of information (AoI) for the dual-queue update system. The numerical results show that compared with the single-queue update system, the average PAoI of the dual-queue update system is reduced by 33.5% and the average AoI dropped by 37.5%.

关键词： Closed-form solutions Markov processes Reliability theory Information age Sensor systems Real-time systems Sensors

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Resistive Memory-based Neural Differential Equation Solver for Score-based Diffusion Model

arXiv

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arXiv 2024年

作者： Yang, Jichang Chen, Hegan Chen, Jia Wang, Songqi Wang, Shaocong Yu, Yifei Chen, Xi Wang, Bo Zhang, Xinyuan Cui, Binbin Li, Yi Lin, Ning Xu, Meng Li, Yi Xu, Xiaoxin Qi, Xiaojuan Wang, Zhongrui Zhang, Xumeng Shang, Dashan Wang, Han Liu, Qi Cheng, Kwang-Ting Liu, Ming Department of Electrical and Electronic Engineering the University of Hong Kong Hong Kong ACCESS – AI Chip Center for Emerging Smart Systems InnoHK Centers Hong Kong Science Park Hong Kong Laboratory of Microelectronic Devices and Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing100029 China State Key Laboratory of Integrated Chips and Systems Frontier Institute of Chip and System Fudan University Shanghai200433 China Institute of the Mind the University of Hong Kong Hong Kong University of Chinese Academy of Sciences Beijing100049 China School of Integrated Circuits Hubei Key Laboratory for Advanced Memories Huazhong University of Science and Technology Wuhan430074 China Department of Electronic and Computer Engineering the Hong Kong University of Science and Technology Hong Kong

Human brains image complicated scenes when reading a novel. Replicating this imagination is one of the ultimate goals of AI-Generated Content (AIGC). However, current AIGC methods, such as score-based diffusion, are still deficient in terms of rapidity and efficiency. This deficiency is rooted in the difference between the brain and digital computers. Digital computers have physically separated storage and processing units, resulting in frequent data transfers during iterative calculations, incurring large time and energy overheads. This issue is further intensified by the conversion of inherently continuous and analog generation dynamics, which can be formulated by neural differential equations, into discrete and digital operations. Inspired by the brain, we propose a time-continuous and analog in-memory neural differential equation solver for score-based diffusion, employing emerging resistive memory. The integration of storage and computation within resistive memory synapses surmount the von Neumann bottleneck, benefiting the generative speed and energy efficiency. The closed-loop feedback integrator is time-continuous, analog, and compact, physically implementing an infinite-depth neural network. Moreover, the software-hardware co-design is intrinsically robust to analog noise. We experimentally validate our solution with 180 nm resistive memory in-memory computing macros. Demonstrating equivalent generative quality to the software baseline, our system achieved remarkable enhancements in generative speed for both unconditional and conditional generation tasks, by factors of 64.8 and 156.5, respectively. Moreover, it accomplished reductions in energy consumption by factors of 5.2 and 4.1. Our approach heralds a new horizon for hardware solutions in edge computing for generative AI applications. © 2024, CC BY-NC-SA.

关键词： Diffusion

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Continuous-Time Digital Twin with Analogue Memristive Neural Ordinary Differential Equation Solver

arXiv

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arXiv 2024年

作者： Chen, Hegan Yang, Jichang Chen, Jia Wang, Songqi Wang, Shaocong Wang, Dingchen Tian, Xinyu Yu, Yifei Chen, Xi Lin, Yinan He, Yangu Wu, Xiaoshan Li, Yi Zhang, Xinyuan Lin, Ning Xu, Meng Li, Yi Zhang, Xumeng Wang, Zhongrui Wang, Han Shang, Dashan Liu, Qi Cheng, Kwang-Ting Liu, Ming Department of Electrical and Electronic Engineering The University of Hong Kong Hong Kong ACCESS – AI Chip Center for Emerging Smart Systems InnoHK Centers Hong Kong Science Park Hong Kong Institute of the Mind The University of Hong Kong Hong Kong Key Laboratory of Microelectronic Devices & Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing100029 China University of Chinese Academy of Sciences Beijing100049 China School of Integrated Circuits Hubei Key Laboratory for Advanced Memories Huazhong University of Science and Technology Wuhan430074 China State Key Laboratory of Integrated Chips and Systems Frontier Institute of Chip and System Fudan University Shanghai200433 China Department of Electronic and Computer Engineering The Hong Kong University of Science and Technology Hong Kong

Digital twins, the cornerstone of Industry 4.0, replicate real-world entities through computer models, revolutionising fields such as manufacturing management and industrial automation. Recent advances in machine learning provide data-driven methods for developing digital twins using discrete-time data and finite-depth models on digital computers. However, this approach fails to capture the underlying continuous dynamics and struggles with modelling complex system behaviour. Additionally, the architecture of digital computers, with separate storage and processing units, necessitates frequent data transfers and Analogue-Digital (A/D) conversion, thereby significantly increasing both time and energy costs. Here, we introduce a memristive neural ordinary differential equation (ODE) solver for digital twins, which is capable of capturing continuous-time dynamics and facilitates the modelling of complex systems using an infinite-depth model. By integrating storage and computation within analogue memristor arrays, we circumvent the von Neumann bottleneck, thus enhancing both speed and energy efficiency. We experimentally validate our approach by developing a digital twin of the HP memristor, which accurately extrapolates its nonlinear dynamics, achieving a 4.2-fold projected speedup and a 41.4-fold projected decrease in energy consumption compared to state-of-the-art digital hardware, while maintaining an acceptable error margin. Additionally, we demonstrate scalability through experimentally grounded simulations of Lorenz96 dynamics, exhibiting projected performance improvements of 12.6-fold in speed and 189.7-fold in energy efficiency relative to traditional digital approaches. By harnessing the capabilities of fully analogue computing, our breakthrough accelerates the development of digital twins, offering an efficient and rapid solution to meet the demands of Industry 4.0. © 2024, CC BY-NC-SA.

关键词： Energy utilization

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Efficient and accurate neural field reconstruction using resistive memory

arXiv

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arXiv 2024年

作者： Yu, Yifei Wang, Shaocong Zhang, Woyu Zhang, Xinyuan Wu, Xiuzhe He, Yangu Yang, Jichang Zhang, Yue Lin, Ning Wang, Bo Chen, Xi Wang, Songqi Zhang, Xumeng Qi, Xiaojuan Wang, Zhongrui Shang, Dashan Liu, Qi Cheng, Kwang-Ting Liu, Ming Department of Electrical and Electronic Engineering The University of Hong Kong Hong Kong Hong Kong ACCESS – AI Chip Center for Emerging Smart Systems InnoHK Centers Hong Kong Science Park Hong Kong Hong Kong Institute of Mind The University of Hong Kong Hong Kong Hong Kong Key Lab of Fabrication Technologies for Integrated Circuits Institute of Microelectronics Chinese Academy of Sciences Beijing100029 China Laboratory of Microelectronic Devices and Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing100029 China University of Chinese Academy of Sciences Beijing100049 China Frontier Institute of Chip and System Fudan University Shanghai200433 China Department of Electronic and Computer Engineering The Hong Kong University of Science and Technology Hong Kong Hong Kong

Human beings construct perception of space by integrating sparse observations into massively interconnected synapses and neurons, offering a superior parallelism and efficiency. Replicating this capability in AI finds wide applications in medical imaging, AR/VR, and embodied AI, where input data is often sparse and computing resources are limited. However, traditional signal reconstruction methods on digital computers face both software and hardware challenges. On the software front, difficulties arise from storage inefficiencies in conventional explicit signal representation. Hardware obstacles include the von Neumann bottleneck, which limits data transfer between the CPU and memory, and the limitations of CMOS circuits in supporting parallel processing. We propose a systematic approach with software-hardware co-optimizations for signal reconstruction from sparse inputs. Software-wise, we employ neural field to implicitly represent signals via neural networks, which is further compressed using low-rank decomposition and structured pruning. Hardware-wise, we design a resistive memory-based computing-in-memory (CIM) platform, featuring a Gaussian Encoder (GE) and an MLP Processing Engine (PE). The GE harnesses the intrinsic stochasticity of resistive memory for efficient input encoding, while the PE achieves precise weight mapping through a Hardware-Aware Quantization (HAQ) circuit. We demonstrate the system’s efficacy on a 40nm 256Kb resistive memory-based in-memory computing macro, achieving 31.5×, 35.5×, and 47.2× energy efficiency improvements and 10.8×, 38.8×, and 6.2× parallelism improvements without compromising reconstruction quality in tasks like 3D CT sparse reconstruction, novel view synthesis, and novel view synthesis for dynamic scenes. This work advances the AI-driven signal restoration technology and paves the way for future efficient and robust medical AI and 3D vision applications. Copyright © 2024, The Authors. All rights reserved.

关键词： Signal reconstruction

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Random resistive memory-based deep extreme point learning machine for unified visual processing

arXiv

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arXiv 2023年

作者： Wang, Shaocong Gao, Yizhao Li, Yi Zhang, Woyu Yu, Yifei Wang, Bo Lin, Ning Chen, Hegan Zhang, Yue Jiang, Yang Wang, Dingchen Chen, Jia Dai, Peng Jiang, Hao Lin, Peng Zhang, Xumeng Qi, Xiaojuan Xu, Xiaoxin So, Hayden Wang, Zhongrui Shang, Dashan Liu, Qi Cheng, Kwang-Ting Liu, Ming Department of Electrical and Electronic Engineering The University of Hong Kong Hong Kong Key Laboratory of Microelectronic Devices & Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing100029 China ACCESS - AI Chip Center for Emerging Smart Systems InnoHK Centers Hong Kong Science Park Hong Kong University of Chinese Academy of Sciences Beijing100049 China Frontier Institute of Chip and System Fudan University Shanghai200433 China College of Computer Science and Technology Zhejiang University Zhejiang310027 China Department of Electronic and Computer Engineering The Hong Kong University of Science and Technology Hong Kong

Visual sensors, including 3D LiDAR, neuromorphic DVS sensors, and conventional frame cameras, are increasingly integrated into edge-side intelligent machines. Realizing intensive multi-sensory data analysis directly on edge intelligent machines is crucial for numerous emerging edge applications, such as augmented and virtual reality and unmanned aerial vehicles, which necessitates unified data representation, unprecedented hardware energy efficiency and rapid model training. However, multi-sensory data are intrinsically heterogeneous, causing significant complexity in the system development for edge-side intelligent machines. In addition, the performance of conventional digital hardware is limited by the physically separated processing and memory units, known as the von Neumann bottleneck, and the physical limit of transistor scaling, which contributes to the slowdown of Moore's law. These limitations are further intensified by the tedious training of models with ever-increasing sizes. In this study, we propose a novel hardware-software co-design, random resistive memory-based deep extreme point learning machine (DEPLM), that offers efficient unified point set analysis. Data-wise, the multi-sensory data are unified as point sets and can be processed universally. Software-wise, most weights of deep extreme point learning machines are exempted from training, which significantly reduce training complexity. Hardware-wise, nanoscale resistive memory not only enables collocation of memory and processing, mitigating the von Neumann bottleneck and the slowdown of Moore's law, but also leverages the inherent programming stochasticity for generating the random and sparse weights of the DEPLM, which also lessens the impact of read noise. We demonstrate the system's versatility across various data modalities and two different learning tasks. Compared to a conventional digital hardware-based system, our co-design system achieves 5.90×, 21.04×, and 15.79× energy efficiency improv

关键词： Cost reduction

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Pruning random resistive memory for optimizing analogue AI

arXiv

引用

arXiv 2023年

作者： Li, Yi Wang, Songqi Zhao, Yaping Wang, Shaocong Zhang, Woyu He, Yangu Lin, Ning Cui, Binbin Chen, Xi Zhang, Shiming Jiang, Hao Lin, Peng Zhang, Xumeng Qi, Xiaojuan Wang, Zhongrui Xu, Xiaoxin Shang, Dashan Liu, Qi Cheng, Kwang-Ting Liu, Ming Department of Electrical and Electronic Engineering The University of Hong Kong Hong Kong Laboratory of Microelectronic Devices & Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing100029 China ACCESS – AI Chip Center for Emerging Smart Systems InnoHK Centers Hong Kong Science Park Hong Kong State Key Lab of Fabrication Technologies for Integrated Circuits Institute of Microelectronics Chinese Academy of Sciences Beijing100029 China Frontier Institute of Chip and System Fudan University Shanghai200433 China College of Computer Science and Technology Zhejiang University Zhejiang310027 China Department of Electronic and Computer Engineering The Hong Kong University of Science and Technology Hong Kong University of Chinese Academy of Sciences Beijing100049 China Institute of Mind The University of Hong Kong Hong Kong

The rapid advancement of artificial intelligence (AI) has been marked by the large language models exhibiting human-like intelligence. However, these models also present unprecedented challenges to energy consumption and environmental sustainability, which are exacerbated by the increasing number of users and the development of even larger models. One promising solution is to revisit analogue computing, a technique that predates digital computing and exploits emerging analogue electronic devices, such as resistive memory, which features in-memory computing, high scalability, and nonvolatility that addresses the von Neumann bottleneck, slowdown of Moore’s law, and volatile DRAM of conventional digital hardware. However, analogue computing still faces the same challenges as before: programming nonidealities and expensive programming due to the underlying devices physics. Therefore, leveraging the efficiency advantage while mitigating the programming disadvantage of analogue computing with resistive memory is a major open problem in AI hardware and electronics communities. Here, we report a universal solution, software-hardware co-design using structural plasticity-inspired edge pruning to optimize the topology of a randomly weighted analogue resistive memory neural network. Software-wise, the topology of a randomly weighted neural network is optimized by pruning connections rather than precisely tuning resistive memory weights. Hardware-wise, we reveal the physical origin of the programming stochasticity using transmission electron microscopy, which is leveraged for large-scale and low-cost implementation of an overparameterized random neural network containing high-performance sub-networks. We implemented the co-design on a 40nm 256K resistive memory macro, observing 17.3% and 19.9% accuracy improvements in image and audio classification on FashionMNIST and Spoken digits datasets, as well as 9.8% (2%) improvement in PR (ROC) in image segmentation on DRIVE datasets, r

关键词： Energy utilization

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