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检索条件"机构=Microelectronics System Design Laboratory Department of Electrical and Computer Engineering"

共 155 条记录，以下是41-50 订阅

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Conditional techniques for low power consumption flip-flops

Conditional techniques for low power consumption flip-flops

引用

IEEE International Conference on Electronics, Circuits and systems (ICECS)

作者： N. Nedovic M. Aleksic V.G. Oklobdzija Department of Electrical and Computer Engineering Advanced Computer System Design Laboratory University of California Davis CA USA

Conditional capture and conditional precharge techniques for high-performance flip-flops are reviewed in terms of power and delay. It is found that application of conditional techniques can improve energy-delay product for up to 14% for 50% input activity and save more than 50% in power consumption for quiet input. This property makes conditional methods suitable for high-performance VLSI systems.

关键词： Energy consumption Flip-flops Clocks Delay Very large scale integration Sampling methods Power engineering computing Laboratories Application software Cooling

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Hybrid latch flip-flop with improved power efficiency

Hybrid latch flip-flop with improved power efficiency

引用

Symposium on Integrated Circuits and systems design (SBCCI)

作者： N. Nedovic V.G. Oklobdzija Advanced Computer System Design Laboratory Department of Electrical and Computer Engineering University of California Davis CA USA

An improved design of a hybrid latch flip-flop is presented. The proposed design overcomes the problem of the glitch at the output and reduces the power consumption and delay of the circuit resulting in a total power-delay-product improvement of about 20%. It also exhibits better soft-clock edge properties compared to the original circuit. This is accomplished by careful design of keeper elements and introducing the feedback path to suppress unnecessary transitions in the circuit. The new design introduces an insignificant area increase.

关键词： Flip-flops Latches Energy consumption Delay Feedback circuits Power dissipation Clocks Power engineering computing Laboratories State feedback

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Introducing RapidHDL: A New Library to design FPGA Hardware in Microsoft. Net and Automatically Generate Verilog Netlists

Introducing RapidHDL: A New Library to Design FPGA Hardware ...

引用

IEEE International Conference on Electro-Information Technology

作者： Jacob N. Allen Hoda S. Abdel-aty-zohdy Robert L. Ewing Microelectronics System Design Lab Department of Electrical and Computer Engineering Oakland University Rochester MI USA Information Directorate Air Force Research Laboratory USA

RapidHDL is introduced as a new object oriented hardware description library for C# developers. RapidHDL seeks to speed up FPGA development by applying best practices used in software engineering to increase productivity. Logic is rapidly defined in component classes using a structure of truth-table definitions, sink nodes, source nodes, and pass-through nodes. Hardware simulation co-runs with C# programs, and a linked-list of clock events simulates propagation delays. A standardized testing framework allows the developer to write test benches, hardware, and software in a single language. Algorithms are presented to automatically transform RapidHDL objects to Verilog netlist that can be synthesized by calling 3rd party tools

关键词： Field programmable gate arrays Hardware design languages Software libraries Object oriented modeling Discrete event simulation Software testing Best practices Software engineering Productivity Logic

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Rendering Adaptation to Address Communication and Computation Constraints in Cloud Mobile Gaming

Rendering Adaptation to Address Communication and Computatio...

引用

2010 IEEE Global Telecommunications Conference GLOBECOM 2010

作者： Shaoxuan Wang Sujit Dey Mobile System Design Laboratory Department of Electrical and Computer Engineering University of California San Diego USA

A new Cloud Mobile Gaming (CMG) approach, where the responsibility of executing the gaming engines, including the most compute intensive tasks of graphic rendering, is put on cloud servers instead of the mobile devices, has the potential for enabling mobile users to play the same rich Internet games available to PC users. However, the mobile gaming user experience may be limited by the communication constraint imposed by available wireless networks and computation constraint imposed by the cost and availability of cloud servers. In this paper, we propose a rendering adaptation technique which can adapt the game rendering parameters to satisfy CMG communication and computation constraints, such that the overall mobile gaming user experience is maximized. Experiments conducted on a commercial UMTS network demonstrate that the proposed rendering adaptation techniques can make the CMG approach feasible: ensuring protection against wireless network conditions, and ensuring server computation scalability, thereby ensuring acceptable mobile gaming user experience.

关键词： Rendering (computer graphics) Games Servers Mobile communication Engines Graphics processing unit

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Video caching in Radio Access Network: Impact on delay and capacity

Video caching in Radio Access Network: Impact on delay and c...

引用

IEEE Conference on Wireless Communications and Networking

作者： Hasti Ahlehagh Sujit Dey Mobile System Design Laboratory Department of Electrical and Computer Engineering University of California San Diego USA

In this paper, we introduce distributed caching of videos at the base-stations of the Radio Access Network (RAN) as a way to reduce the need to bring requested videos from Internet CDNs, thereby reducing backhaul transmission, improving video quality of experience - delay and video stalling - and increasing overall network capacity to support more number of simultaneous video requests. Unlike Internet CDNs that can store millions of videos in a relatively few large sized caches, our proposed caching architecture consists of a very large number of micro-caches, with each base-station micro-cache being able to store only 1000s of videos, and hence may not be able to have high cache hit ratio. To address this challenge, we propose two new caching policies based on the User Preference Profile (UPP) of users in a cell: R-UPP (Reactive UPP) and P-UPP (Proactive UPP). Further, for videos that result in cache misses and need to be fetched from Internet CDNs, we develop a video scheduling approach that allocates the RAN backhaul resources to the video requests so as to reduce video latency and increase network capacity. We develop a discrete event statistical simulation framework using MATLAB to study the performance of RAN caching. Our simulation results show that RAN micro-caches with the proposed UPP-based caching policies, together with the proposed scheduling approach, can improve the probability of video requests that can meet initial delay requirements by almost 60%, and the number of concurrent video requests that can be served by up to 100%. The results also show that UPP based policies can enhance network capacity by up to 30% compared to conventional caching policies.

关键词： Delay Radio access networks Streaming media Internet Bandwidth Mobile communication Wireless networks

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Plasticity recurrent spiking neural networks for olfactory pattern recognition

Plasticity recurrent spiking neural networks for olfactory p...

引用

Midwest Symposium on Circuits and systems (MWSCAS)

作者： J.N. Allen H.S. Abdel-Aty-Zohdy R.L. Ewing Microelectronics System Design Laboratory Department of Electrical and System Engineering Oakland University Rochester MI USA Information Directorate Air Force Research Laboratory OH USA

This paper introduces a novel spiking neural network methodology, and applies it to an odorant learning and detection application. Spike-time dependent plasticity can support coding schemes that are based on spatio-temporal spike patterns. Spiking (or pulsed) neural networks (SNNs) are models which explicitly take into account the timing of inputs. The network input and output are usually represented as series of spikes (delta function or more complex shapes). Plasticity SNNs have an advantage of being able to recurrently process information. Spike-time dependent plasticity can enhance signal transmission by selectively strengthening synaptic connections that transmit precisely timed spikes at the expense of those synapses that transmit poorly timed spikes. Complete theory describes the spiking network's digital implementation. Theory is verified using simulation of a biologically plausible odor environment with 1023 odor receptor inputs. Stochastic on-chip learning uses sampling and a correlation filter to learn odors despite noisy environment conditions. Simulation and Verilog chip design are tested on a field programmable gate array. A scalable field programmable gate array implementation with 1024 inputs, 1 output, and expansion capability for unlimited outputs is synthesized into 87,062 gates

关键词： Neural networks Recurrent neural networks Olfactory Pattern recognition Biological system modeling Field programmable gate arrays Timing Shape Stochastic processes Sampling methods

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Exploring the biocomputing frontier

Exploring the biocomputing frontier

引用

Midwest Symposium on Circuits and systems (MWSCAS)

作者： R.L. Ewing H.S. Abdel-Aty-Zohdy F. Schuermeyer L. Liou J.B. Moncrief M. Rubeiz M. Williamson Air Force Research Laboratory OH USA Microelectronics System Design Laboratory Department of Electrical and System Engineering Oakland University Rochester MI USA Department of Electrical Engineering Wright State University Dayton OH USA

Stop thinking that the universe is best described by Boolean order operations, consider the world of biocomputing. The idea in exploring the multidimensional characteristics of biocomputing systems involves multilevel protein logic interaction with hybrid digital systems (bio/digital/analog systems). In the protein biocomputing world, all models are multilevel and nonlinear exponential in nature. These biocomputing systems are linearized by boundary limited frequency, time response and dimensional ranges. The protein model and its correct development is probably the most difficult aspect for biocomputing issues. Previous protein models were not dealing with 2 and 3 dimensional models, while the current protein models are now faced with high frequency design, due to the emergence of bio-nanodevices. These future biocomputing devices will be chemical sensors, fluidic computer systems, optical switches, nanoactuators, self-repairing polymorphic computing systems, cognitive processors and biorobotics

关键词： Frequency Optical computing Multidimensional systems Logic Digital systems Time factors Protein engineering Chemical sensors Optical switches Nanoscale devices

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A DLL-regulated SIMO power converter for DVS-enabled power-aware VLSI systems

A DLL-regulated SIMO power converter for DVS-enabled power-a...

引用

Midwest Symposium on Circuits and systems (MWSCAS)

作者： Rajdeep Bondade Dongsheng Ma Integrated System Design Laboratory Department of Electrical & Computer Engineering University of Arizona Tucson Tucson AZ USA

A delay-locked loop (DLL) regulated single-inductor multiple-output (SIMO) power converter is presented. It takes advantage of the fast phase locking property of a DLL to identify the SIMO converter's regulation errors between the output voltages and their corresponding references. In response to these errors, an adaptive peak current modulation technique is proposed to adjust the instantaneous duty ratios, and thus minimize the regulation errors in the converter. The DLL acquires locking within 350 ns, allowing it to respond to load dynamics promptly, which is very desirable for DVS-enabled power-efficient VLSI systems. The system was designed and simulated in IBM 130-nm CMOS process. Fully transistor-based HSPICE simulations show that, with a 1.8 V nominal input supply, the converter precisely regulates two independent output voltages at 0.9 V and 1.5 V, respectively. It achieves the maximum efficiency of 87.2% at a total power of 104.8 mW and a switching frequency of 500 kHz.

关键词： Very large scale integration Pulse width modulation Error correction Voltage control Delay Inductors Integrated circuit noise DC-DC power converters Network-on-a-chip Power dissipation

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Digitally controlled integrated pseudo-CCM SIMO converter with adaptive freewheel current modulation

Digitally controlled integrated pseudo-CCM SIMO converter wi...

引用

Annual IEEE Conference on Applied Power Electronics Conference and Exposition (APEC)

作者： Yi Zhang Dongsheng Ma Integrated System Design Laboratory Department of Electrical and Computer Engineering University of Arizona Tucson Tucson AZ USA

ISBN: (纸本)9781424447824

In this paper, a digitally controlled integrated single-inductor multiple-output (SIMO) converter operating in pseudo-CCM (PCCM) mode is presented. With an adaptive freewheel current modulation (AFCM) technique, conduction loss of the freewheel switch is significantly reduced in unbalanced load conditions. Moreover, cross-regulation and switching noise are both effectively restricted. A prototype of a single-inductor dual-output (SIDO) boost converter was designed with a 130-nm CMOS process. The two outputs are regulated at 2.5 V and 1.8 V respectively, at a switching frequency of 500 KHz. The simulation results indicate that the expectant specifications are well implemented.

关键词： Digital control Programmable control Adaptive control Digital modulation Inductors Switches Switching converters Control systems Dynamic voltage scaling DC-DC power converters

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Integrated switched-capacitor voltage doubler with clock transition periods boosting and transfer blocking techniques

Integrated switched-capacitor voltage doubler with clock tra...

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Annual IEEE Conference on Applied Power Electronics Conference and Exposition (APEC)

作者： Phong Ngo Dongsheng Ma Integrated System Design Laboratory Department of Electrical and Computer Engineering University of Arizona Tucson Tucson AZ USA

In this paper, a CMOS switched-capacitor voltage doubler is proposed. It employs the techniques of clock synchronization and charge transfer blocking to minimize the reversion loss. The clock transition period detection and boosting circuit modules allow continuous charge action to the output node, which significantly improves operation performances. The proposed voltage doubler was designed using IBM 180 nm CMOS process, with a 1.2 V supply voltage. Under no-load condition, it achieves 99.92% of ideal voltage level with 8 mV voltage ripple, while consuming only 9.6 ¿W of quiescent power. With a load ranging from 20 k¿ to 200 k¿, the up-conversion ratio performs 45% better than the prior arts.

关键词： Clocks Boosting Charge transfer Switching converters Charge pumps Power supplies Timing Capacitors Threshold voltage Topology

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