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51st Midwest Symposium on Circuits and systems (MWSCAS 2008), vol.2

作者： Robert L. Ewing Hoda S. Abdel-Aty-Zohdy Michael C. Hollenbeck Kenneth S. Stevens Information Directorate US Air Force Research Laboratory OH USA Microelectronics System Design Laboratory Department of Electrical and Systems Engineering Oakland University Rochester MI USA Department of Electrical and Computer Engineering University of Utah Salt Lake UT USA

Fractional-order systems have applications in the areas of Flight Control, Robotics, Missile Guidance, Control of Structural Vibrations of Space Platforms and Sensor Technology. Fractional-order transfer functions can characterize complex nonlinear dynamics with many fewer parameters than integer-order functions. This paper addresses the use of a polymer-electrolyte transistor (PET) for use in implementating fractional-order algorithms for signal processing. The PET's advantage over the conventional RC and RL circuits is that it can be both functionally scaled and varied for dynamic fractional-order parameter controllability.

关键词： Fractional-Order Signal Processing Polymer-electrolyte transistor Acid/base chemistry Diffusion Electrokinetic flow

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ANN digitally programmable analog synapse

ANN digitally programmable analog synapse

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Midwest Symposium on Circuits and systems (MWSCAS)

作者： M. Al-Nsour H. Abdel-Aty-Zhody Microelectronics System Design Laboratory Department of Electrical and Systems Engineering Oakland University Rochester MI USA Oakland University Rochester MI US

An Artificial Neural Network (ANN) synapse with local digital weight storage capability is presented. It utilizes a novel, compact, voltage mode multiplying digital-to-analog converter to perform multiplication between an analog input and a digital weight. A 6-bit signed weight synapse chip has been implemented in VLSI through MOSIS 1.2 micrometer n-well CMOS technology. It occupies a total area of 1.35 mm/sup 2/. With +3 Volts supply, the circuit accepts analog inputs within /spl plusmn/1 V. Output is also within /spl plusmn/1 V. Maximum power consumption is 20 mW and total error is less than 3%. Circuit analysis and performance evaluation is presented.

关键词： Voltage Circuits Artificial neural networks Digital-analog conversion CMOS technology Energy consumption Silicon Capacitance microelectronics Laboratories

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Thermal Stress and Reliability Analysis of TSV-Based 3-D ICs With a Novel Adaptive Strategy Finite Element Method

Thermal Stress and Reliability Analysis of TSV-Based 3-D ICs...

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作者： Zhou, Hao Zhu, Hengliang Cui, Tao Pan, David Z. Zhou, Dian Zeng, Xuan State Key Laboratory of ASIC and Systems Department of Microelectronics Fudan University Shanghai200433 China State Key Laboratory of Scientific and Engineering Computing National Center for Mathematics and Interdisciplinary Sciences Institute of Computational Mathematics Academy of Mathematics and System Sciences Chinese Academy of Sciences Beijing100190 China Department of Electrical and Computer Engineering University of Texas at Austin AustinTX78712 United States Department of Electrical Engineering University of Texas at Dallas RichardsonTX75080 United States

Thermomechanical stress is one of the most important issues in performance and reliability analysis of through silicon via-based 3-D integrated circuits (3-D ICs), where an accurate numerical approach is generally needed to produce stress models and identify weak points in the structure. In this paper, we propose a knowledge-oriented nonuniform (KONU) refinement strategy for 3-D IC stress simulation under the framework of a parallel adaptive finite element method (FEM), and apply it in 3-D IC stress and reliability analysis. Parallel adaptive FEM is promising for solving large-scale problems due to its high accuracy and parallel efficiency. It produces refined meshes based on the a posteriori error analysis, which has the quasi-optimal convergence rate for solving the problem. It has high parallel efficiency, which makes it suitable for handling large and complex structures in 3-D ICs. The KONU refinement strategy developed in this paper can efficiently reduce the number of refinement iterations in parallel adaptive FEM for 3-D IC thermomechanical stress simulation and improves the computational efficiency. It is demonstrated in this paper through several examples that parallel adaptive FEM for thermomechanical stress evaluation can be widely applied in 3-D IC reliability analysis, where accurate stress simulation and modeling is exceptionally important to produce accurate results. © 2018 IEEE.

关键词： Reliability analysis

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Low power discrete voltage assignment under clock skew scheduling 11

Low power discrete voltage assignment under clock skew sched...

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Asia and South Pacific design Automation Conference

作者： Li Li Jian Sun Yinghai Lu Hai Zhou Xuan Zeng Electrical Engineering and Computer Science Department Northwestern University USA State Key Laboratory of ASIC & System Microelectronics Department Fudan University China

ISBN: (纸本)9781424475162

Multiple Supply Voltage (MSV) assignment has emerged as an appealing technique in low power IC design, due to its flexibility in balancing power and performance. However, clock skew scheduling, which has great impact on criticality of combinational paths in sequential circuit, has not been explored in the merit of MSV assignment. In this paper, we propose a discrete voltage assignment algorithm for sequential circuit under clock scheduling. The sequential MSV assignment problem is first formulated as a convex cost dual network flow problem, which can be optimally solved in polynomial time assuming delay of each gate can be chosen in continuous domain. Then a mincut-based heuristic is designed to convert the unfeasible continuous solution into feasible discrete solution while largely preserving the global optimality. Besides, we revisit the hardness of the general discrete voltage assignment problem and point out some misunderstandings on the approximability of this problem in previous related work. Benchmark test for our algorithm shows 9.2% reduction in power consumption on average, in compared with combinational MSV assignment. Referring to the continuous solution obtained from network flow as the lower bound, the gap between our solution and the lower bound is only 1.77%.

关键词： Delay Clocks Logic gates Power demand Sequential circuits Scheduling

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Baseband analog front-end and digital back-end for reconfigurable multi-standard terminals

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IEEE Circuits and systems Magazine 2006年第1期6卷 8-26页

作者： Baschirotto, A. Castello, Rinaldo Campi, Fabio Cesura, Giovanni Toma, Mario Guerrieri, Roberte Lodi, Andrea Lavagno, Luciano Malcovati, Piero Department of Electronics University of Pavia Italy STMicroelectronics Italy Advanced Research Center on Electronic Systems University of Bologna Italy Department of Electronics Politecnico di Torino Italy Department of Electrical Engineering University of Pavia Italy Department of Central Research and Development ST Microelectronics Italy Bologna Italy Department of Electronics University of Pavia Italy Italy Solid State Circuit Society IEEE Italy IEEE Italy Semiconductor Laboratory Max Planck Institute of Terrestrial and Extrater- Restrial Physics Munich Germany New IP and Design Support of the Computer and Peripheral Group of ST-Microelectronics University of Bologna Italy Politecnico di Torino Italy Cadence Berkeley Laboratories United States STMicroelectronics Italy Bologna Italy Department of Electrical Engineering University of Pavia Italy CR and D ST-Microelectronics Agrate Brianza Italy

Multimedia applications are driving wireless network operators to add high-speed data services such as Edge (E-GPRS), WCDMA (UMTS) and WLAN (IEEE 802.11a,b,g) to the existing network. This creates the need for multi-mode cellular handsets that support a wide range of communication standards, each with a different RF freguency, signal bandwidth, modulation scheme, etc. This in turn generates several design challenges for the analog and digital building blocks of the physical layer. In addition to the above-mentioned protocols, mobile devices often include Bluetooth, GPS, FM-radio and TV services that can work concurrently with data and voice communication. Multi-mode, multi-band, and multi-standard mobile terminals must satisfy all these different reguirements. Sharing and/or switching transceiver building blocks in these handsets is mandatory in order to extend battery life and/or to reduce cost. Only adaptive circuits that are able to reconfigure themselves within the handover time can meet the design reguirements of a single receiver or transmitter covering all the different standards while ensuring seamless inter-interoperability. This paper presents analog and digital base-band circuits that are able to support GSM (with Edge), WCDMA (UMTS), WLAN and Bluetooth using reconfigurable building blocks. The blocks can trade off power consumption for performance on the fly, depending on the standard to be supported and the reguired QoS (Quality of Service) level. © 2006 IEEE.

关键词： computer terminals

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Topologically Protected Wavelength Conversion in a Photonic Valley Hall Insulator

Topologically Protected Wavelength Conversion in a Photonic ...

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CLEO: Science and Innovations in CLEO 2024, CLEO: S and I 2024 - Part of Conference on Lasers and Electro-Optics

作者： Sohn, Byoung-Uk Choi, Ju Won Chen, George F.R. Gao, Hongwei Mitchell, William J. Ng, Doris K.T. Tan, Dawn T.H. Photonics Devices and System Group SUTD-MIT International Design Center Singapore University of Technology and Design Singapore487372 Singapore NanoFab Facility Electrical and Computer Engineering Department University of California Santa Barbara Santa BarbaraCA93106 United States Institute of Microelectronics A*STAR 2 Fusionopolis Way #08-02 Innovis Tower Singapore138634 Singapore

We explore nonlinear effects in a topological photonic valley Hall insulator with a Kagome system at telecommunications wavelengths, we achieve topologically protected -12dB parametric conversion with sub-milliwatt in... 详细信息

关键词： Landforms

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Topologically Protected Wavelength Conversion in a Photonic Valley Hall Insulator

Topologically Protected Wavelength Conversion in a Photonic ...

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2024 Conference on Lasers and Electro-Optics, CLEO 2024

ISBN: (纸本)9781957171395

关键词： Photonics

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Efficient test generation for built-in self-test boundary-scan template

Efficient test generation for built-in self-test boundary-sc...

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VLSI Test Symposium

作者： P. Nagvajara M.G. Karpovsky L.B. Levitin Department of Electrical and Computer Engineering Drexel University Philadelphia PA USA Research Laboratory for Design and Testing of Computer and Communication Systems Department of Electrical Computer and System Engineering Boston University Boston MA USA

An analysis and design of a pseudorandom pattern generator, (PRPG), based on a linear recurrence, for built-in self-test (BIST) boundary scan design is presented. The authors present for the case when r>or=s, a design of an s-stage PRPG capable of producing 2/sup s/-1 distinct r-bit patterns within 2/sup s/-1 clock pulses independent of the hardware realization of the PRPG. For the case when r >

关键词： Automatic testing Built-in self-test Circuit testing Clocks Test pattern generators Pulse generation Pattern analysis Laboratories system testing design engineering

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Map Based Indoor Robot Navigation and Localization Using Laser Range finder

Map Based Indoor Robot Navigation and Localization Using Las...

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International Conference on Control, Automation, Robotics and Vision

作者： Shung Han Cho Sangjin Hong Department of Electrical and Computer Engineering Mobile System Design Laboratory Stony Brook University - SUNY Stony Brook NY USA

ISBN: (纸本)9781424478149

This paper presents a map based robot navigation and localization algorithm using laser range finder for indoor environments. A navigation path is given by the sequence of grids and global map information is represented by the list of vertexes. The grid based navigation facilities path planning as well as complements localization with priori information of the grid sequence. The pattern of vertexes is represented by distance, adjacency, and slant among them for the comparison between map information and range data. A mobile robot is globally localized by finding the matched pattern between the set of vertexes from the map and the set of vertexes from the range data. The proposed method is verified with actual range data from laser range finder.

关键词： map representation indoor robot navigation localization laser range finder

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Random force based algorithm for local minima escape of potential field method

Random force based algorithm for local minima escape of pote...

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International Conference on Control, Automation, Robotics and Vision (ICARCV)

作者： Jinseok Lee Yunyoung Nam Sangjin Hong Department of Electrical and Computer Engineering Mobile System Design Laboratory Stony Brook University-SUNY Stony Brook NY USA

We address a new inherent limitation of potential field methods, which is symmetrically aligned robot-obstacle-goal (SAROG). The SAROG involves one critical risk of local minima trap. For dealing with the problem, we investigate the way how the local minima trap is recognized, and present our random force algorithm. The force algorithm has two categories of random unit total force (RUTF) and random unit total force with repulsion removal (RUTF-RR) which are selected based on the conditions of a robot, an obstacle and a goal.

关键词： Force Collision avoidance Robot kinematics Robot sensing systems Mobile robots Oscillators

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