Multiple Supply Voltage (MSV) assignment has emerged as an appealing technique in low power IC design, due to its flexibility in balancing power and performance. However, clock skew scheduling, which has great impact ...
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ISBN:
(纸本)9781424475162
Multiple Supply Voltage (MSV) assignment has emerged as an appealing technique in low power IC design, due to its flexibility in balancing power and performance. However, clock skew scheduling, which has great impact on criticality of combinational paths in sequential circuit, has not been explored in the merit of MSV assignment. In this paper, we propose a discrete voltage assignment algorithm for sequential circuit under clock scheduling. The sequential MSV assignment problem is first formulated as a convex cost dual network flow problem, which can be optimally solved in polynomial time assuming delay of each gate can be chosen in continuous domain. Then a mincut-based heuristic is designed to convert the unfeasible continuous solution into feasible discrete solution while largely preserving the global optimality. Besides, we revisit the hardness of the general discrete voltage assignment problem and point out some misunderstandings on the approximability of this problem in previous related work. Benchmark test for our algorithm shows 9.2% reduction in power consumption on average, in compared with combinational MSV assignment. Referring to the continuous solution obtained from network flow as the lower bound, the gap between our solution and the lower bound is only 1.77%.
CP measurements show that PBTI stress induced interface trap area density ΔN it in InGaAs/Al 2 O 3 n-MOSFET is very small and has power law time evolution At 0.22 in the stress phase, and is partially recovered in...
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CP measurements show that PBTI stress induced interface trap area density ΔN it in InGaAs/Al 2 O 3 n-MOSFET is very small and has power law time evolution At 0.22 in the stress phase, and is partially recovered in the recovery phase. However the DC I s -V g measurements show large degradations of negative ΔV g and sub-threshold swing S in the sub-threshold region and are recovered in the recovery phase, also show degradation of positive ΔV g in the on-current region and continuing degradation in the recovery phase until reaching a stable state. The I s -V g degradation is mainly contributed by generation of near interface slow oxide traps under stress with recoverable donor trap energy density ΔD SOX DONOR in the InGaAs energy gap with a tail extended to the conduction band energy, and permanent acceptor trap energy density ΔD SOX ACCEPTOR in the conduction band energy with a tail extended to the energy gap. This trap model explains all experimental details perfectly.
This paper develops a systematic procedure of designing global power system stabilizers (GPSSs) based on collocated control to enhance the damping during interarea oscillations. The availability of remote signals from...
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ISBN:
(纸本)9781457710001
This paper develops a systematic procedure of designing global power system stabilizers (GPSSs) based on collocated control to enhance the damping during interarea oscillations. The availability of remote signals from phasor measurement units (PMUs) enables the wide-area control in large scale systems. The closed loop eigenvalues are excluded from a region of the complex plane by the collocated control algorithm guaranteeing that low frequency modes must be damped. The optimum locations for GPSSs were selected using controllability. The damping performance of a 16-machine, 68-bus study system reinforced with GPSSs is examined in the frequency and time domains. The simulation results show that the control scheme is able to damp out interarea oscillations following possible disturbances.
Rapid HDL is an object oriented software library for scripting the generation of synthesizable Verilog. A fully functional customized microprocessor is defined and automatically synthesized for an FPGA from an XML spe...
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Rapid HDL is an object oriented software library for scripting the generation of synthesizable Verilog. A fully functional customized microprocessor is defined and automatically synthesized for an FPGA from an XML specification file. Using a library of blocks, a microprocessor fabric is defined in XML. Control states specify the connections between the fabric blocks during microprocessor operation. Opcodes sequence the control states and provide a vocabulary for assembly programs, which are compiled and executed on the microprocessor.
A new Cloud Mobile Gaming (CMG) approach, where the responsibility of executing the gaming engines, including the most compute intensive tasks of graphic rendering, is put on cloud servers instead of the mobile device...
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A new Cloud Mobile Gaming (CMG) approach, where the responsibility of executing the gaming engines, including the most compute intensive tasks of graphic rendering, is put on cloud servers instead of the mobile devices, has the potential for enabling mobile users to play the same rich Internet games available to PC users. However, the mobile gaming user experience may be limited by the communication constraint imposed by available wireless networks and computation constraint imposed by the cost and availability of cloud servers. In this paper, we propose a rendering adaptation technique which can adapt the game rendering parameters to satisfy CMG communication and computation constraints, such that the overall mobile gaming user experience is maximized. Experiments conducted on a commercial UMTS network demonstrate that the proposed rendering adaptation techniques can make the CMG approach feasible: ensuring protection against wireless network conditions, and ensuring server computation scalability, thereby ensuring acceptable mobile gaming user experience.
In this paper, a CMOS switched-capacitor voltage doubler is proposed. It employs the techniques of clock synchronization and charge transfer blocking to minimize the reversion loss. The clock transition period detecti...
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In this paper, a CMOS switched-capacitor voltage doubler is proposed. It employs the techniques of clock synchronization and charge transfer blocking to minimize the reversion loss. The clock transition period detection and boosting circuit modules allow continuous charge action to the output node, which significantly improves operation performances. The proposed voltage doubler was designed using IBM 180 nm CMOS process, with a 1.2 V supply voltage. Under no-load condition, it achieves 99.92% of ideal voltage level with 8 mV voltage ripple, while consuming only 9.6 ¿W of quiescent power. With a load ranging from 20 k¿ to 200 k¿, the up-conversion ratio performs 45% better than the prior arts.
In this paper, a digitally controlled integrated single-inductor multiple-output (SIMO) converter operating in pseudo-CCM (PCCM) mode is presented. With an adaptive freewheel current modulation (AFCM) technique, condu...
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ISBN:
(纸本)9781424447824
In this paper, a digitally controlled integrated single-inductor multiple-output (SIMO) converter operating in pseudo-CCM (PCCM) mode is presented. With an adaptive freewheel current modulation (AFCM) technique, conduction loss of the freewheel switch is significantly reduced in unbalanced load conditions. Moreover, cross-regulation and switching noise are both effectively restricted. A prototype of a single-inductor dual-output (SIDO) boost converter was designed with a 130-nm CMOS process. The two outputs are regulated at 2.5 V and 1.8 V respectively, at a switching frequency of 500 KHz. The simulation results indicate that the expectant specifications are well implemented.
This paper presents a map based robot navigation and localization algorithm using laser range finder for indoor environments. A navigation path is given by the sequence of grids and global map information is represent...
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ISBN:
(纸本)9781424478149
This paper presents a map based robot navigation and localization algorithm using laser range finder for indoor environments. A navigation path is given by the sequence of grids and global map information is represented by the list of vertexes. The grid based navigation facilities path planning as well as complements localization with priori information of the grid sequence. The pattern of vertexes is represented by distance, adjacency, and slant among them for the comparison between map information and range data. A mobile robot is globally localized by finding the matched pattern between the set of vertexes from the map and the set of vertexes from the range data. The proposed method is verified with actual range data from laser range finder.
We address a new inherent limitation of potential field methods, which is symmetrically aligned robot-obstacle-goal (SAROG). The SAROG involves one critical risk of local minima trap. For dealing with the problem, we ...
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We address a new inherent limitation of potential field methods, which is symmetrically aligned robot-obstacle-goal (SAROG). The SAROG involves one critical risk of local minima trap. For dealing with the problem, we investigate the way how the local minima trap is recognized, and present our random force algorithm. The force algorithm has two categories of random unit total force (RUTF) and random unit total force with repulsion removal (RUTF-RR) which are selected based on the conditions of a robot, an obstacle and a goal.
This article presents an optimized thermal stepper system which is used to align the critical parts of high-performance smart sensors, such as capacitive sensors. In order to apply the system in harsh and inaccessible...
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This article presents an optimized thermal stepper system which is used to align the critical parts of high-performance smart sensors, such as capacitive sensors. In order to apply the system in harsh and inaccessible industrial environments, improvements have been made, such as reduced power consumption (1mW during measurement mode), increased alignment accuracy (within 0.1um), increased interconnect reliability, and better immunity to external interferences. Experimental results are shown which demonstrate the improved performance of the thermal stepper system.
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