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Midwest Symposium on Circuits and systems (MWSCAS)

作者： F.A. El-Licy H.S. Abdel-Aty-Zohdy Department of Information and Computer Science Institute of Statistical Studies and Research Cairo University Egypt Microelectronics System Design Laboratory Electrical and Systems Engineering Oakland University MI USA

A hierarchical approach for the abstraction of digital VLSICs is presented. Circuit layout is hierarchically abstracted into logical constructs of binary tree structures, which may be manipulated to extract circuit functionality for the purpose of verifying design correctness. VLSIC design specification in the form of HDL is hierarchically decomposed to generate logical formulae for the given specification. By comparing the above, a verification report is obtained

关键词： Formal verification Logic design Binary trees Hardware design languages Production Very large scale integration electrical capacitance tomography Combinational circuits Data structures Boolean functions

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Novel radio frequency energy harvesting model

Novel radio frequency energy harvesting model

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2012 IEEE International Power engineering and Optimization Conference, PEOCO 2012

作者： ElAnzeery, Hossam Mahmoud Gamal ElDin Mohammed ElBagouri, Mohamed Abd ElAziz Saad Guindi, Rafik Department of Microelectronics System Design Nanoelectronics Integrated Systems Center Nile University Smart Village B2 Km 28 Cairo-Alex. Desert Road 12677 Cairo Egypt Department of Electrical and Electronics Engineering University of Technology PETRONAS Bandar Seri Iskandar 31750 Tronoh Perak Malaysia

ISBN: (纸本)9781467306614

Energy and Environment, both are the main concern for every researcher allover the world. Alternative energy sources that are environmental friendly became the challenge to satisfy world needs. Oil and Gas are no more the main source of Energy, consequently the demand of an everlasting cheap source of energy that is environmental friendly, is the main goal recently. During the last decade, power consumption has decreased opening the field for energy harvesting to become a real time solution for providing different sources of electrical power. Energy Harvesting is a new technology that is going to make a revolution in the coming decade. Energy Harvesting is a technique to provide alternative sources of energy that are environmental friendly and low in cost. Future applications need wireless devices to operate for longer durations away from centralized power sources or the amount of power that can be supplied to these wireless devices to be increased. Currently, many technologies have been developed that attempt to overcome the limitations imposed on wireless devices. Radio Frequency Energy Harvesting is one of these types of energy harvesting that is able to convert Radio Frequency waves from ambient air to electrical energy. This paper presents a model for harvesting radio frequency energy waves. The presented model is directed towards different applications and targeting mainly Radio Frequency Identification (RFID) applications, where it works on frequencies in the range of 2.1 - 2.45 GHz. The recommended model faces size and efficiency problems presenting a very small radio frequency energy-harvesting model that can be implemented easily inside Radio Frequency Identification (RFID) applications. A final model for Radio Frequency Energy Harvesting is proposed based on different types of simulations and experiments. © 2012 IEEE.

关键词： Energy harvesting

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Intelligent information processing using neural networks and genetic algorithms

Intelligent information processing using neural networks and...

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Midwest Symposium on Circuits and systems (MWSCAS)

作者： H.S. Abdel-Aty-Zohdy R.L. Ewing Microelectronics System Design Laboratory Electrical and Systems Engineering Oakland University Rochester MI USA U.S. Air Force Research Laboratory Dayton OH USA

Intelligent information processing (IIP) or the smart processing of signals in communication systems and data measurements from multi-sensor systems are needed for advanced microautonomous applications. A balanced combination of efficient algorithms, fast networks, and collaboration of the different technologies are required for smaller, faster, and more efficient system-on-a-chip applications. In this paper we present guidelines/approach for intelligent information processing using neural networks (NNs) and genetic algorithms (GAs) which are capable of learning through discovery and/or reinforcement with features optimization through chromosome mutations of GAs. Specific details about a special application for electronic-nose (EN) implementation to discriminate among four chemicals, using reinforcement NN implemented tiny-chip and a GA system implementation is presented with test results.

关键词： Intelligent networks Information processing Neural networks Signal processing Collaboration system-on-a-chip Guidelines Genetic algorithms Biological cells Genetic mutations

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A genetic algorithm tracking model for product deployment in telecom services

A genetic algorithm tracking model for product deployment in...

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Midwest Symposium on Circuits and systems (MWSCAS)

作者： L. Murphy H.S. Abdel-Aty-Zohdy M. Hashem-Sherif Microelectronics System Design Laboratory Electrical and Systems Engineering Oakland University Rochester MI USA AT and T Bell Laboratories Inc. Middletown NJ USA

Genetic algorithms (GA) are designed to search for, discover and emphasize good solutions by applying selection and crossover techniques, inspired by nature, to supply solutions to engineering systems. Genetic algorithms operate on pieces of information like nature does on genes in the course of evolution. All individuals of one generation are evaluated by a fitness function. This paper presents an approach to implement a genetic algorithm to depict a recently developed "Integrated Model" for defect tracking for product deployment in telecommunication systems by means of a solution space representing target variables. The genetic algorithm inputs these target values as dynamic input measurements. From these measurements, the best possible fused values are found for the target variables. The goal of the genetic algorithm is dynamically to update the parameters applied to the input measurements to find the optimum solution for the defect tracking model system. Focus will be given to one dimension of sensor input measurements consisting of three four-bit binary sensor inputs varying within a given range of data points. The genetic algorithm is applied to these inputs by means of a 64 6-bit random member binary population using the "half-sibling and a clone" (HSAC) technique of crossover and mutation. The population members are evaluated using a fitness function where the fittest individuals are retained to survive and produce offspring for the next generation and the remainder is discarded. Genetic diversity is maintained through using a roulette wheel technique. The simulation tool MATLAB will be used to simulate the genetic algorithm. The genetic algorithm will be completed in VLSI using Verilog and the Mentor Graphics tools. The first stage components have been designed and completed using the Mentor Graphics toolset

关键词： Genetic algorithms Telecommunication services Mathematical model Target tracking Graphics Algorithm design and analysis Genetic engineering design engineering systems engineering and theory Cloning

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Fractional-Order Signal Processing using a Polymer-Electrolyte Transistor

Fractional-Order Signal Processing using a Polymer-Electroly...

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51st Midwest Symposium on Circuits and systems (MWSCAS 2008), vol.2

作者： Robert L. Ewing Hoda S. Abdel-Aty-Zohdy Michael C. Hollenbeck Kenneth S. Stevens Information Directorate US Air Force Research Laboratory OH USA Microelectronics System Design Laboratory Department of Electrical and Systems Engineering Oakland University Rochester MI USA Department of Electrical and Computer Engineering University of Utah Salt Lake UT USA

Fractional-order systems have applications in the areas of Flight Control, Robotics, Missile Guidance, Control of Structural Vibrations of Space Platforms and Sensor Technology. Fractional-order transfer functions can characterize complex nonlinear dynamics with many fewer parameters than integer-order functions. This paper addresses the use of a polymer-electrolyte transistor (PET) for use in implementating fractional-order algorithms for signal processing. The PET's advantage over the conventional RC and RL circuits is that it can be both functionally scaled and varied for dynamic fractional-order parameter controllability.

关键词： Fractional-Order Signal Processing Polymer-electrolyte transistor Acid/base chemistry Diffusion Electrokinetic flow

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Thermal Stress and Reliability Analysis of TSV-Based 3-D ICs With a Novel Adaptive Strategy Finite Element Method

Thermal Stress and Reliability Analysis of TSV-Based 3-D ICs...

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作者： Zhou, Hao Zhu, Hengliang Cui, Tao Pan, David Z. Zhou, Dian Zeng, Xuan State Key Laboratory of ASIC and Systems Department of Microelectronics Fudan University Shanghai200433 China State Key Laboratory of Scientific and Engineering Computing National Center for Mathematics and Interdisciplinary Sciences Institute of Computational Mathematics Academy of Mathematics and System Sciences Chinese Academy of Sciences Beijing100190 China Department of Electrical and Computer Engineering University of Texas at Austin AustinTX78712 United States Department of Electrical Engineering University of Texas at Dallas RichardsonTX75080 United States

Thermomechanical stress is one of the most important issues in performance and reliability analysis of through silicon via-based 3-D integrated circuits (3-D ICs), where an accurate numerical approach is generally needed to produce stress models and identify weak points in the structure. In this paper, we propose a knowledge-oriented nonuniform (KONU) refinement strategy for 3-D IC stress simulation under the framework of a parallel adaptive finite element method (FEM), and apply it in 3-D IC stress and reliability analysis. Parallel adaptive FEM is promising for solving large-scale problems due to its high accuracy and parallel efficiency. It produces refined meshes based on the a posteriori error analysis, which has the quasi-optimal convergence rate for solving the problem. It has high parallel efficiency, which makes it suitable for handling large and complex structures in 3-D ICs. The KONU refinement strategy developed in this paper can efficiently reduce the number of refinement iterations in parallel adaptive FEM for 3-D IC thermomechanical stress simulation and improves the computational efficiency. It is demonstrated in this paper through several examples that parallel adaptive FEM for thermomechanical stress evaluation can be widely applied in 3-D IC reliability analysis, where accurate stress simulation and modeling is exceptionally important to produce accurate results. © 2018 IEEE.

关键词： Reliability analysis

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Cognitive processing using spiking neural networks

Cognitive processing using spiking neural networks

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IEEE National Conference on Aerospace and Electronics (NAECON)

作者： Jacob N. Allen Hoda S. Abdel-Aty-Zohdy Robert L. Ewing Microelectronics System Design Laboratory Department of Electrical and Computer Engineering Oakland University Rochester Hills MI USA Air Force Research Laboratory OH USA

ISBN: (纸本)9781424444946

Powerful parallel cognitive processors can be developed by studying biologically plausible models of cognitive systems in animals and extrapolating key principles to be adapted for implementation in digital computer architectures. The network described here uses basic statistical methods such as proportion sampling on a massively parallel scale to create a general purpose pattern classifier. From these principles, we can achieve auto association and self organization that provides fundamental cognitive processing. Signal preprocessing is essential to transform the signal into a scale and rotation invariant binary pattern. The network avoids the curse of dimensionality by filtering out irrelevant inputs, allowing us to combine large sensor input vectors from multiple sources. Recent hardware designs define the network structure and state in memory, and then use accelerator processor cores to modify these memory structures in parallel.

关键词： Neural networks Neurons Biological system modeling Biology computing Biological information theory Brain modeling Computer architecture microelectronics Power engineering and energy Biosensors

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Agile hardware development with rapid hardware definition language

Agile hardware development with rapid hardware definition la...

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IEEE International Conference on Electro-Information Technology

Rapid HDL is a hardware definition language developed in C# for the Microsoft .Net platform. Rapid HDL unifies digital FPGA hardware development and co-software integration. Hardware is scripted using reusable software objects, communication between hardware and software is automatic, and synthesis is automated using a free tool chain. Rapid HDL represents 18,000 lines of code and is freely available under the MIT license.

关键词： Hardware design languages Software libraries Testing Licenses microelectronics Force sensors Field programmable gate arrays Software reusability Software tools High level languages

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Baseband analog front-end and digital back-end for reconfigurable multi-standard terminals

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IEEE Circuits and systems Magazine 2006年第1期6卷 8-26页

作者： Baschirotto, A. Castello, Rinaldo Campi, Fabio Cesura, Giovanni Toma, Mario Guerrieri, Roberte Lodi, Andrea Lavagno, Luciano Malcovati, Piero Department of Electronics University of Pavia Italy STMicroelectronics Italy Advanced Research Center on Electronic Systems University of Bologna Italy Department of Electronics Politecnico di Torino Italy Department of Electrical Engineering University of Pavia Italy Department of Central Research and Development ST Microelectronics Italy Bologna Italy Department of Electronics University of Pavia Italy Italy Solid State Circuit Society IEEE Italy IEEE Italy Semiconductor Laboratory Max Planck Institute of Terrestrial and Extrater- Restrial Physics Munich Germany New IP and Design Support of the Computer and Peripheral Group of ST-Microelectronics University of Bologna Italy Politecnico di Torino Italy Cadence Berkeley Laboratories United States STMicroelectronics Italy Bologna Italy Department of Electrical Engineering University of Pavia Italy CR and D ST-Microelectronics Agrate Brianza Italy

Multimedia applications are driving wireless network operators to add high-speed data services such as Edge (E-GPRS), WCDMA (UMTS) and WLAN (IEEE 802.11a,b,g) to the existing network. This creates the need for multi-mode cellular handsets that support a wide range of communication standards, each with a different RF freguency, signal bandwidth, modulation scheme, etc. This in turn generates several design challenges for the analog and digital building blocks of the physical layer. In addition to the above-mentioned protocols, mobile devices often include Bluetooth, GPS, FM-radio and TV services that can work concurrently with data and voice communication. Multi-mode, multi-band, and multi-standard mobile terminals must satisfy all these different reguirements. Sharing and/or switching transceiver building blocks in these handsets is mandatory in order to extend battery life and/or to reduce cost. Only adaptive circuits that are able to reconfigure themselves within the handover time can meet the design reguirements of a single receiver or transmitter covering all the different standards while ensuring seamless inter-interoperability. This paper presents analog and digital base-band circuits that are able to support GSM (with Edge), WCDMA (UMTS), WLAN and Bluetooth using reconfigurable building blocks. The blocks can trade off power consumption for performance on the fly, depending on the standard to be supported and the reguired QoS (Quality of Service) level. © 2006 IEEE.

关键词： Computer terminals

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XML defined custom microprocessors using Rapid Hardware Definition Language

XML defined custom microprocessors using Rapid Hardware Defi...

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IEEE National Conference on Aerospace and Electronics (NAECON)

Rapid HDL is an object oriented software library for scripting the generation of synthesizable Verilog. A fully functional customized microprocessor is defined and automatically synthesized for an FPGA from an XML specification file. Using a library of blocks, a microprocessor fabric is defined in XML. Control states specify the connections between the fabric blocks during microprocessor operation. Opcodes sequence the control states and provide a vocabulary for assembly programs, which are compiled and executed on the microprocessor.

关键词： Microprocessors Hardware design languages Hardware XML Registers Fabrics Software

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