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B-system: New solution for seamlessly interconnecting track-side and on-board systems over network

Hitachi Review 2005年第4期54卷 169-173页

作者： Koiwa, Hiroaki Ito, Satoru Matsuo, Masakazu Okura, Yoshinori Ishifuji, Tomoaki Ebata, Tomoichi System Solution Department Transportation System Division Industrial Systems Rolling Stock Electrical Systems Design Department Mito Transportation Systems Product Division Industrial Systems Transportation Control Systems Engineering Department Transportation Information Systems Division Information and Telecommunication Systems Systems Research Department Hitachi Research Laboratory Wireless Radio System Division Central Research Laboratory 4th Research Department Systems Development Laboratory

The fundamental concept of the ubiquitous information society is the ability to obtain needed information whenever and wherever one wants. In the context of enhanced railway passenger services, this means above all providing passengers with access to the network anytime and anywhere whether in railway stations or on-board trains. Equally important considering the greater intelligence of railcars themselves, is the need for more advanced on-board operating systems that are seamlessly connected to track-side systems. As a comprehensive rail system integrator, Hitachi has responded to these needs and at the same time contributed to more convenient and efficient rail systems through the development of a sophisticated broadband network system for trains - dubbed the B-system - that not only significantly increases the capacity of on-board networks but also supports seamless continuous interconnection between on-board and track-side systems.

关键词： Railroad transportation

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Continuous-time digital twin with analog memristive neural ordinary differential equation solver

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Science Advances 2025年第22期11卷

作者： Hegan Chen Jichang Yang Jia Chen Songqi Wang Shaocong Wang Dingchen Wang Xinyu Tian Yifei Yu Xi Chen Yinan Lin Qifan Zhu Yangu He Xiaoshan Wu Yi Li Xinyuan Zhang Ning Lin Meng Xu Xumeng Zhang Xiaojuan Qi Zhongrui Wang Han Wang Dashan Shang Qi Liu Kwang-Ting Cheng Ming Liu Department of Electrical and Electronic Engineering the University of Hong Kong Hong Kong China. School of Microelectronics Southern University of Science and Technology Shenzhen 518055 China. Center for Advanced Semiconductors and Integrated Circuits the University of Hong Kong Hong Kong China. Department of Electronic and Computer Engineering the Hong Kong University of Science and Technology Hong Kong China. School of Integrated Circuits Hubei Key Laboratory for Advanced Memories Huazhong University of Science and Technology Wuhan 430074 China. State Key Laboratory of Integrated Chips and Systems Frontier Institute of Chip and System Fudan University Shanghai 200433 China. State Key Lab of Fabrication Technologies for Integrated Circuits and Key Laboratory of Microelectronic Devices & Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing 100029 China. University of Chinese Academy of Sciences Beijing 100049 China.

Digital twins, which replicate real-world entities through computational models, are transforming manufacturing and automation. While recent advances in machine learning have enabled data-driven digital twin development using discrete-time data and finite-depth models on digital hardware, these approaches face significant limitations. They struggle to capture continuous-time dynamics and model complex systems, and suffer from substantial time and energy overheads due to physically separated storage and processing as well as frequent analog-digital (A/D) conversions. Here, we propose a memristive neural ordinary differential equation (ODE) solver for digital twins. Our approach is intrinsically time-continuous using infinite-depth neural networks to model complex dynamics. Fully analog memristor arrays collocate storage and computation, addressing the von Neumann bottleneck and reducing A/D conversion requirements. We experimentally validate our solver on digital twins of HP variable-resistor model and Lorenz96 dynamics, demonstrating a 166.5-fold/369.3-fold speedup and a 499.0-fold/673.9-fold improvement in energy efficiency, respectively. This work paves the way to future digital twins for Industry 4.0.

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Paradigm of design for biosystem-on-a-chip(BioSoC)

Paradigm of design for biosystem-on-a-chip(BioSoC)

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IEEE International Conference on Microelectronic systems Education

作者： R.L. Ewing H.S. Abdel-Aty-Zohdy Information Directorate Air Force Research Laboratory Air Force Institute of Technology Department of Electrical and Computer Engineering Wright Patterson Air Force Base OH USA Microelectronics System Design Laboratory Department of Electrical and Systems Engineering Oakland University Rochester MI USA

The paradigm of design for biosystem-on-a-chip (BioSoC), is that multidisciplinary skills are required. Thus, the educational goals are to develop an understanding of micro/macro collaboration along with the ability to apply and use multidisciplinary skills for the design and performance evaluation of a "biosystem on a chip". The need for the architectural design of the BioSoC addresses the next-generation of intelligent information processing systems.

关键词： Intelligent sensors Collaboration design engineering Biology computing Chemical and biological sensors Biosensors Artificial intelligence microelectronics Circuits Chemical sensors

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Introducing RapidHDL: A New Library to design FPGA Hardware in Microsoft. Net and Automatically Generate Verilog Netlists

Introducing RapidHDL: A New Library to Design FPGA Hardware ...

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IEEE International Conference on Electro-Information Technology

作者： Jacob N. Allen Hoda S. Abdel-aty-zohdy Robert L. Ewing Microelectronics System Design Lab Department of Electrical and Computer Engineering Oakland University Rochester MI USA Information Directorate Air Force Research Laboratory USA

RapidHDL is introduced as a new object oriented hardware description library for C# developers. RapidHDL seeks to speed up FPGA development by applying best practices used in software engineering to increase productivity. Logic is rapidly defined in component classes using a structure of truth-table definitions, sink nodes, source nodes, and pass-through nodes. Hardware simulation co-runs with C# programs, and a linked-list of clock events simulates propagation delays. A standardized testing framework allows the developer to write test benches, hardware, and software in a single language. Algorithms are presented to automatically transform RapidHDL objects to Verilog netlist that can be synthesized by calling 3rd party tools

关键词： Field programmable gate arrays Hardware design languages Software libraries Object oriented modeling Discrete event simulation Software testing Best practices Software engineering Productivity Logic

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Dynamic scheduling issues in SMT architectures

Dynamic scheduling issues in SMT architectures

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International Symposium on Parallel and Distributed Processing (IPDPS)

作者： Chulho Shin Seong-Won Lee J.-L. Gaudiot Samsung Electronics Corporation System Design Technology Laboratory Department of Electrical Engineering-Systems University of Southern California USA Department of Electrical Engineering and Computer Science University of California Irvine USA

Simultaneous multithreading (SMT) attempts to attain higher processor utilization by allowing instructions from multiple independent threads to coexist in a processor and compete for shared resources. Previous studies have shown, however, that its throughput may be limited by the number of threads. A reason is that a fixed thread scheduling policy cannot be optimal for the varying mixes of threads it may face in an SMT processor. Our adaptive dynamic thread scheduling (ADTS) was previously proposed to achieve higher utilization by allowing a detector thread to make use of wasted pipeline slots with nominal hardware and software costs. The detector thread adaptively switches between various fetch policies. Our previous study showed that a single fixed thread scheduling policy presents much room (some 30%) for improvement compared to an oracle-scheduled case. In this paper, we take a closer look at ADTS. We implemented the functional model of the ADTS and its software architecture to evaluate various heuristics for determining a better fetch policy for a next scheduling quantum. We report that performance could be improved by as much as 25%.

关键词： Dynamic scheduling Surface-mount technology Yarn Processor scheduling Detectors Multithreading Throughput Face detection Adaptive scheduling Pipelines

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Multifractal processing of speech signals

Multifractal processing of speech signals

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International Conference on Information, Communications and Signal Processing

作者： A.Z.R. Langi K. Soemintapura W. Kinsner Laboratory of Microelectronics Design Institute of Technology Bandung InterUniversity Microelectronics Centre Bandung West Java Indonesia Laboratory for Signals and Systems Department of Electrical Engineering Institute of Technology Bandung West Java Indonesia Department of Electrical and Computer Engineering University of Manitoba Winnipeg MAN Canada

This paper describes a novel framework in processing speech signals using multifractality concepts, and shows that multifractality could be a new fundamental tool for speech processing. New approaches using the self-similarity model of complexity have been developed to simplify processing of complicated speech signals. The approaches associate signals with fractal sets and then characterize the sets using real numbers called fractal dimensions. This paper extends the approaches by associating speech signals with measures and then characterizing the measures with multifractal curves such as Mandelbrot dimensions (denoted as f(/spl alpha/)) or Renyi dimensions D/sub q/. Such curves (also known as singularity curves) are the characterization of speech signals. This paper shows that multifractal (or singularity) processing of speech is capable of providing important processing aspects: decomposition, representation, and spectrum characterization-a capability that makes Fourier processing of signals is fundamental. The multifractal approach can decompose speech into various segments based on variations of the segment's Holder exponents. The results can be used for new speech segmentation schemes. The multifractal approach is also used in characterizing speech through singularity spectrum. This can be used to develop better accuracy speech recognition schemes. Finally, the paper describes a process to reconstruct speech signals from their singularity representation, by the means of the so-called wavelet maxima.

关键词： Fractals Speech processing Signal processing Speech recognition Laboratories microelectronics Fourier transforms Time measurement Signal design Java

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A wavelet-based measurement of signal fractal dimensions

A wavelet-based measurement of signal fractal dimensions

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Canadian Conference on electrical and Computer engineering (CCECE)

作者： A.Z.R. Langi H.B. Nugraha Laboratory for Signals and Systems Department of Electrical Engineering and IC Design Laboratory IURC Microelectronics DSP Research and Technology Group Bandung Institute of Technology Bandung Jawa Barat Indonesia

This paper describes a study of measuring signal fractal dimensions (especially in a form of Lipschitz exponents /spl gamma/) using wavelets. The procedure is as follows. Given a one-dimensional signal f(t) and its corresponding wavelet transform (at a scale a and a position b) as W/sub f/(a, b), we find wavelet maxima lines l(a, b) and their corresponding wavelet maxima |W/sub f/(a, b)|. Suppose the signal f(t) has a Lipschitz exponent /spl gamma/ at t=b/sub 0/, and there is a maxima line l(a,b) reaching b/sub 0/ as a/spl rarr/0. The corresponding wavelet maxima in the line satisfy an inequality |W/sub f/(a, b)|/spl les/Ca/sup /spl gamma/+0.5/ for some constant C and a/spl rarr/0. A log-log plot on the inequality estimates the Lipschitz exponent /spl gamma/. We have performed an experiment of the procedure for f(t)=1-|0.5-t|/sup /spl gamma//, where the Lipschitz component /spl gamma/ varies from 0.1 to 0.9 at a 0.1 interval. The procedure provides relatively good estimates for 0.5/spl les//spl gamma//spl les/0.9, with relative errors less them 10%.

关键词： Fractals Wavelet transforms Signal processing Laboratories Signal processing algorithms Digital signal processing Microwave integrated circuits Signal design microelectronics Electric variables measurement

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Board-level diagnosis by signature analysis

Board-level diagnosis by signature analysis

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IEEE International Test Conference

作者： M.G. Karpovsky P. Nagvajara Research Laboratory for Design and Testing of Computer and Communication Systems Computer and Communication Systems Computer and Communication Systems Department of Electrical Computer and System Engineering Boston University Boston MA USA

Board-level diagnostic techniques by signature analysis based on single-error-correcting Hamming codes over GF(2/sup M/) (where M is the number of outputs per chip) are presented. Two techniques are considered: the space-time compressor technique for the case when responses from N chips on the board are wired to the compressor; and the time compressor technique for the case when test responses from each chip are transferred to the compressor via system bus. Assuming a single-faulty-chip model, a faulty chip on the board under test is located by an analysis of the relationship between the distortions in the obtained signatures. Both techniques for board-level diagnosis require less hardware than the straightforward diagnostic techniques using a built-in signature analyzer for every chip or selective testing of each chip via the system bus, hence offering an efficient approach for a design of a built-in-self-test board for for manufacturing testing.< >

关键词： system testing system buses Hardware Built-in self-test Automatic testing Pattern analysis Fault diagnosis Laboratories design engineering systems engineering and theory

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Analog signal-selector circuit for quick gas detection from gas-sensor arrays

Analog signal-selector circuit for quick gas detection from ...

引用

Midwest Symposium on Circuits and systems (MWSCAS)

作者： H.S. Abdel-Aty-Zohdy F.A. El-Licy Dept. of Electr. & Syst. Eng. Oakland Univ. Rochester MI USA Microelectronics System Design Laboratory Department of Electrical and Systems Engineering Oakland University Rochester MI USA

A Sixteen Input Maximum/Minimum Analog signal-selector Circuit (SIMMAC) is designed, simulated, and implemented using 2 /spl mu/m p-well (Orbit) CMOS technology. The circuit is useful in recognition of gas types from measurements of thin-film gas-sensor arrays. The output signal of each thin-film gas detector is typically a function of bias voltages, temperature and pressure, film type, frequency, and gas type. Gas sensor arrays provide profiles of resistivity vs. temperature, for a particular PPM, and/or profiles of resistivity vs. pressure at a particular temperature. Since different chemical gas types have peak resistivity values at a certain temperature and a certain pressure, a selector circuit is needed to identify chemical gas components. The SIMMAC design is based on a multiple-input current comparator median circuit. Simulation results gave an accuracy of better than 94% with analog input signal values from 1.6 to 3.6 V. The SIMMAC is suitable for gas detection from a sensor-array of up to 16-elements with known models and negligible signal distortion. Further, it may be used as a post processor to select the winning synapse in an unsupervised neural network for pattern recognition with distorted and unidentified models of gas mixtures.

关键词： Temperature sensors Conductivity Circuit simulation CMOS technology Thin film circuits Gas detectors Sensor arrays Chemicals Signal design CMOS analog integrated circuits

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Domain distributed intelligent processing for information fuselets

Domain distributed intelligent processing for information fu...

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IEEE International Symposium on Circuits and systems (ISCAS)

作者： R.L. Ewing H.S. Abdel-Aty-Zohdy US Air Force Research Laboratory Information Directorate Air Force Institute of Technology Dayton OH USA Dept of Electrical & Systems Engineering Microelectronics System Design Laboratory Oakland University Rochester MI USA

ISBN: (纸本)0780366859

The best solution for one intelligent information fusion design is obviously domain specific and not universal. This is especially true in multidisciplinary design domains of information systems at higher clock speeds where the need arises to distribute the intelligent processing requirements between the digital circuit elements and their real world interconnects in the mixed-signal sensor domain. In this paper we propose the distribution of intelligent processing, or fuselets by three levels of information fusion. These are; perception, fuselets, processing algorithms and neural nets. The proposed robust design methodology for multidisciplinary levels, involves the blending of the s-domain (continuous) and z-domain (digital), resulting in the wp-domain (mixed-signal) models. The advantage of using the wp-domain bilinear transformation for mixed-signal design is the ability to handle the discrete portion of the design like a continuous system, thus unifying the design process for domain distributed intelligent processing systems.

关键词： Intelligent sensors Information systems Clocks Digital circuits Integrated circuit interconnections Sensor systems Neural networks Robustness design methodology Continuous time systems

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