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Improving the ductility of laser directed energy deposited borated stainless steel by increasing laser power

Journal of Manufacturing Processes 2025年 145卷 494-507页

作者： Huang, Sheng Li, Qingyu Zhang, Xiaoyu Cui, Bin Li, Dichen Zhang, Anfeng Miao, Kai State Key Laboratory for Manufacturing Systems Engineering School of Mechanical Engineering Xi'an Jiaotong University Xi'an710049 China Science and Technology on Reactor System Design Technology Laboratory Nuclear Power Institute of China Chengdu610213 China Department of Mechanical and Electrical Engineering Yuncheng University Yuncheng044000 China Co. Ltd. Chengdu610091 China

Borated stainless steels (BSSs) are extensively applied in the nuclear energy industry due to boron's excellent thermal neutron absorption capacity, but large and brittle borides formed during casting result in a low ductility. Here, a BSS was produced by laser directed energy deposition, and an investigation was conducted to analyze the impact of laser power on both the microstructure and mechanical properties of the deposited material. Fibrous borides with relatively low volume fraction in the overlapping zone resulted in higher ductility, while lamellar borides with relatively large volume fraction in the non-overlapping zone led to higher strength. As the laser power increased from 180 W to 330 W, the size of fibrous and lamellar eutectic borides and austenite increased significantly, the width of the soft overlapping zone increased by 2.27 times, and the elongation increased by 2.03 times, although yield strength and ultimate tensile strength decreased by 46.3 % and 31.7 %, respectively. As a result, these findings confirmed the feasibility of significantly improving the ductility of the as-deposited BSS by increasing the laser power. The work here provides a way to tailoring the mechanical properties of BSS produced by laser additive manufacturing. © 2025 The Society of Manufacturing Engineers

关键词： Ductility

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Lightweight Task-Oriented Semantic Communication Empowered by Large-Scale AI Models

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IEEE Transactions on Vehicular Technology 2025年

作者： Liu, Chuanhong Guo, Caili Yang, Yang Chen, Mingzhe Quek, Tony Q. S. Beijing University of Posts and Telecommunications Beijing Key Laboratory of Network System Architecture and Convergence School of Information and Communication Engineering Beijing100876 China Beijing University of Posts and Telecommunications Beijing Laboratory of Advanced Information Networks School of Information and Communication Engineering Beijing100876 China University of Miami Department of Electrical and Computer Engineering Institute for Data Science and Computing Coral GablesFL United States Singapore University of Technology and Design Dept. of Information Systems Technology and Design 487372 Singapore

Recent studies have focused on leveraging large-scale artificial intelligence (LAI) models to improve semantic representation and compression capabilities. However, the substantial computational demands of LAI models pose significant challenges for real-time communication scenarios. To address this, this paper proposes utilizing knowledge distillation (KD) techniques to extract and condense knowledge from LAI models, effectively reducing model complexity and computation latency. Nevertheless, the inherent complexity of LAI models leads to prolonged inference times during distillation, while their lack of channel awareness compromises the distillation performance. These limitations make standard KD methods unsuitable for task-oriented semantic communication scenarios. To address these issues, we propose a fast distillation method featuring a pre-stored compression mechanism that eliminates the need for repetitive inference, significantly improving efficiency. Furthermore, a channel adaptive module is incorporated to dynamically adjust the transmitted semantic information based on varying channel conditions, enhancing communication reliability and adaptability. In addition, an information bottleneck-based loss function is derived to guide the fast distillation process. Simulation results verify that the proposed scheme outperform baselines in term of task accuracy, model size, computation latency, and training data requirements. © 1967-2012 IEEE.

关键词： NP-hard

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Joint design of Radar Receive Filter and Unimodular ISAC Waveform with Sidelobe Level Control

arXiv

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arXiv 2025年

作者： Zhang, Kecheng Liu, Ya-Feng Wang, Zhongbin Yuan, Weijie Keskin, Musa Furkan Wymeersch, Henk Xia, Shuqiang School of System Design and Intelligent Manufacturing The Shenzhen Key Laboratory of Robotics and Computer Vision Southern University of Science and Technology Shenzhen518055 China State Key Laboratory of Scientific and Engineering Computing Institute of Computational Mathematics and Scientific/Engineering Computing Academy of Mathematics and Systems Science Chinese Academy of Sciences Beijing100190 China Department of Electrical Engineering Chalmers University of Technology Gothenburg41296 Sweden ZTE Corporation The State Key Laboratory of Mobile Network and Mobile Multimedia Technology Shenzhen518055 China

Integrated sensing and communication (ISAC) has been considered a key feature of next-generation wireless networks. This paper investigates the joint design of the radar receive filter and dual-functional transmit waveform for the multiple-input multiple-output (MIMO) ISAC system. While optimizing the mean square error (MSE) of the radar receive spatial response and maximizing the achievable rate at the communication receiver, besides the constraints of full-power radar receiving filter and unimodular transmit sequence, we control the maximum range sidelobe level, which is often overlooked in existing ISAC waveform design literature, for better radar imaging performance. To solve the formulated optimization problem with convex and nonconvex constraints, we propose an inexact augmented Lagrangian method (ALM) algorithm. For each subproblem in the proposed inexact ALM algorithm, we custom-design a block successive upper-bound minimization (BSUM) scheme with closed-form solutions for all blocks of variable to enhance the computational efficiency. Convergence analysis shows that the proposed algorithm is guaranteed to provide a stationary and feasible solution. Extensive simulations are performed to investigate the impact of different system parameters on communication and radar imaging performance. Comparison with the existing works shows the superiority of the proposed algorithm. © 2025, CC BY-NC-SA.

关键词： Mean square error

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PROCESS-DEPENDENT CIRCUIT MODELING AND SIMULATION OF SOIJFETS - DIGITAL VLSI APPLICATIONS

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SIMULATION 1993年第2期60卷 113-126页

作者： ABDELATYZOHDY, HS TALKHAN, IE [o_1]Microelectronics Systems Design Laboratory Department of Electrical and Systems Engineering Oakland University Rochester Michigan 48309-4401 [o_2]Microelectronics Systems Design Laboratory Department of Electrical and Systems Engineering Oakland University Rochester Michigan 48309-4401

Accurate circuit modeling and simulation of Silicon-on-Insulator (SOI) enhancement and depletion Junction Field-Effect transistors (JFETs) is presented. The nonuniformity in FET device parameters along the channel depth (due to fabrication processes), is taken into account. This is typical in SOI and other thin-film structures. Since SOI fabrication processes parameters are represented, in our model, by a closed form nobility variation, improved model accuracy is guaranteed. Simulation results are found to be within less than 3% of actual measurements. Small-signal circuit-model parameters are determined for SOI FJETs and then evaluated for further logic applications. Inverters with a channel Enhancement-JFET (E-JFET) drivers and n-channel depletion-JFET loads (E/D inverters) are also considered with different supply voltage values, device parameters and digital applications.

关键词： PROCESS-DEPENDENT CIRCUIT MODELING AND SIMULATION THIN FILM SILICON-ON INSULATOR JUNCTION FIELD EFFECT TRANSISTORS VLSI LOGIC CIRCUITS ENHANCEMENT-JFETS

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Research on Robust Measurement Method of Heart Rate Using Remote Photoplethysmography Based on Adversarial Learning Network with High and Low Frequency Features

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IEEE Transactions on Circuits and systems for Video Technology 2025年

作者： Zhai, Dezhao Chen, Wei Ding, Yinghao Yu, Ming Li, Qinwei Wu, Hang Tianjin University of Technology Tianjin Key Laboratory for Advanced Mechatronic System Design and Intelligent Control School of Mechanical Engineering Tianjin300384 China National Demonstration Center for Experimental Mechanical and Electrical Engineering Education Tianjin University of Technology China People's Liberation Army Systems Engineering Institute Academy of Military Sciences Tianjin300161 China Civil Aviation University of China Tianjin Key Laboratory for Advanced Signal Processing Tianjin300300 China Nankai University School of Artificial Intelligence Tianjin300381 China

Remote Photoplethysmography (rPPG) is a non-contact method for measuring heart rate (HR) through facial video, breaking the constraints of contact measurements and offering broad application prospects. However, in real monitoring scenarios, the distance of subjects and facial illumination often vary. This leads to degradation of rPPG signals due to changes in facial resolution and light intensity. This paper presents the High and Low Frequency Feature Adversarial Learning Network (HLFF-AL), which utilizes feature space interpolation and composite feature capture to perform multi-band global and local signal extraction. By adopting an adversarial learning strategy, it enhances the capability to capture semantic information of rPPG under varying resolutions and lighting, bridging the differences in rPPG signal generation due to resolution changes. While maintaining accuracy in HR measuring, the robustness of the network is improved to achieve robust measurement of HR via rPPG. Even under high-resolution conditions, the Mean Absolute Error (MAE) for the three public datasets - unchanging lighting (COHFACE, UBFC-rPPG) and varying lighting (BUAA-MIHR) - reached 1.10 bpm, 1.64 bpm, and 4.41 bpm, respectively, with a mere 0.29 bpm difference in MAE between high and low resolutions on the BUAA-MIHR dataset. This demonstrates that HLFF-AL can predict more robust rPPG signals in various resolutions and lighting scenarios, achieving competitive results compared to state-of-the-art methods. © 1991-2012 IEEE.

关键词： Heart

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Energy diffusion model of bR for voxel identification

Energy diffusion model of bR for voxel identification

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2005 IEEE International 48th Midwest Symposium on Circuits and systems, MWSCAS 2005

作者： Neto, Didimo Garcia Abdel-Aty-Zohdy, Hoda S. Microelectronics System Design Laboratory Department of Electrical and Systems Engineering Oakland University Rochester United States

ISBN: (纸本)0780391977

In this paper, a potential biological structure for computer volumetric memory is investigated. Bacteriorhodopsin is a protein found in the purple membrane of the bacteria Halobacterium salinarum. This protein has light absorption properties that generate different stable states allowing the use of multi-level logic as well as binary logic. CHARMm™ has been used to simulate the energy response of Bacteriorhodopsin at room temperature 300K for the bR ground state and the other states. The K state takes place after blue light (λ= 635nm) absorption on the bR state. The energy difference is found to be an increase of 1086.92 kcal/mol which is responsible for triggering the photocycle that also includes the states K, L, M, N, and O. An energy surplus is found between 6 and bR state that may be spread to surrounding molecules. However, conformational interference will not produce photons necessary for the isomerization reaction. Further Quantum Molecular (QM) analysis should provide an extended model for this macromolecular energy study. © 2005 IEEE.

关键词： Storage allocation (computer)

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A hardware implementation of genetic algorithms for measurement characterization

A hardware implementation of genetic algorithms for measurem...

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9th IEEE International Conference on Electronics, Circuits and systems, ICECS 2002

作者： Sharawi, Mohammad S. Quinlan, James Abdel-Aty-Zohdy, Hoda S. Microelectronics System Design Laboratory Electrical and Systems Engineering Oakland University Rochater MI 48309 United States

ISBN: (纸本)0780375963

Integrated circuits that sense, receive, transmit, and process signals are the eye, ears, and nose of the hitechnical field of the millennium. To process/store/analyee signals acquired from sensors, hybrid systems with Rexible and adaptable Intelligent Information Processing and Perception (IIPP) are needed. Genetic Algorithms (GA) present a suitable pre-processing operation hecause of their good convergence to optimum solutions and characterination capabilities. Most of GAs are built via software because of their ease of editing and eustomization. Less attention has been given to hardware implementation of such algorithms. In this paper we present a hardware design approach of a GA for optimum measurements representationjcharacterization to a following IIPP stage. A multilevel verification of the GA is performed via VHDL. In particular the design of efficient universal multipliers and dividers is addressed. A new time efficient approach for Crossover based on preassigned least error value is proposed. The Crossover scheme is called Half Siblings and D Clone. Such a scheme needs 10 iterations to converge the system proposed for sensor measurement characterization. This takes 7680 clock cycles, which is only 96 μsec when implemented in the 0.25 pm CMOS technology. © 2002 IEEE.

关键词： Genetic algorithms

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Verification system interface for VLSI combinational circuits

Verification system interface for VLSI combinational circuit...

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1998 Midwest Symposium on Circuits and systems, MWSCAS 1998

作者： El-Licy, Fatma A. Abdel-Aty-zohdy, Hoda S. Department of Electrical and Systems Engineering Microelectronics System Design Laboratory Oakland University RochesterMI48309-4401 United States

ISBN: (纸本)0818689145

A proof of correctness of a given VLSIC system design is established by proving the consistency and implication of the implemented design with respect to the specified design. The set of conditions that establish such consistency is termed verification conditions (VCs). This paper presents an automatic interface system for the verification of VLSI combinational circuits in which VCs are synthesized from circuit definition. This interface will allow a top down specification of the design (written in a given HDL language) to be parsed into binary tree structure representation. Also, a logical construct is built up from the physical layout specifications of the implemented design (extracted as SPICE file). The top down parse tree along with bottom up logic constructs form the basic building block structure of the front end of the interface system. VCs are then synthesized from the outcomes of the front end through a preprocessor. The back end of the interface system constitutes the preprocessor and a set of designators and modules for manipulating mathematical and logical operations. It provides an environment in which a theorem prover can be used to create a formal proof schema for the VCs which satisfy partial correctness of the circuit under consideration. © 1999 IEEE.

关键词： Specifications

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Implementation of programmable digital sigmoid function circuit for neuro-computing

Implementation of programmable digital sigmoid function circ...

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1998 Midwest Symposium on Circuits and systems, MWSCAS 1998

作者： Al-Nsour, Mahmoud Abdel-Aty-zohdy, Hoda S. Department of Electrical and Systems Engineering Microelectronics Systems Design Laboratory Oakland University RochesterMI48309-4401 United States

ISBN: (纸本)0818689145

A programmable digital sigmoid function generator circuit has been designed and implemented. The circuit is based on second order approximation of the nonlinear sigmoid function and utilizing its characteristics. It offers an easy way of changing the steepness of the function in the transition state. In addition, the squaring function operation was implemented using combinational logic. This offers a compact realization of the system as a parallel bit architecture. The maximum output error is.047 and the average error is within 0.01. Simulations show that the circuit operates satisfactorily up to 50 MHz. The digital VLSI circuit has been fabricated using MOSIS/AMI N-well 1.2 μm CMOS double metal process. It occupies an area of 900×450 μm2. © 1999 IEEE.

关键词： Timing circuits

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Intelligent information processing using neural networks and genetic algorithms

Intelligent information processing using neural networks and...

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43rd Midwest Circuits and systems Conference (MWSCAS-2000)

作者： Abdel-Aty-Zohdy, Hoda S. Ewing, Robert L. Microelectronics System Design Lab. Electrical and Systems Engineering Oakland University Rochester MI 48309 United States

Intelligent Information Processing (IIP) or the smart processing of signals in communication systems and data measurements from multi-sensor systems are needed for advanced micro autonomous applications. A balanced combination of efficient algorithms, fast networks, and collaboration of the different technologies are required for smaller, faster, and more efficient system-on-a-chip applications. In this paper we present guidelines/approach for intelligent information processing using Neural Networks (NNs) and Genetic Algorithms (GAs) which are capable of learning through discovery and/or reinforcement with features optimization through chromosome mutations of GAs. Specific details about a special application for Electronic-Nose (EN) implementation to discriminate among four chemicals, using reinforcement NN implemented tiny-chip and a GA system implementation is presented with test results.

关键词： Intelligent agents

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