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Asilomar Conference on Signals, systems & Computers

作者： H.S. Abdel-Aty-Zohdy A.A. Hiasat Microelectronics System Design LaboratoryDepartment of Electrical and Systems Engineering Oakland University Rochester MI USA

An improved VLSI squaring circuit, for a Viterbi algorithm, is designed and implemented in the n-well CMOS 2/spl mu/m process. It is faster and more area efficient than conventional and table look-up approaches. In addition it compensates for inaccuracies and noise. The new design is based on combinational logic and the implemented chip reduces the IC area by more than 40% and increases the speed by 100%, as compared to other published designs (Eshraghi et al., 1994). design considerations, performance evaluations, and test results are presented.

关键词： Very large scale integration Logic design Combinational circuits CMOS logic circuits Viterbi algorithm microelectronics Laboratories design engineering systems engineering and theory CMOS process

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Multifractal processing of speech signals

Multifractal processing of speech signals

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International Conference on Information, Communications and Signal Processing

作者： A.Z.R. Langi K. Soemintapura W. Kinsner Laboratory of Microelectronics Design Institute of Technology Bandung InterUniversity Microelectronics Centre Bandung West Java Indonesia Laboratory for Signals and Systems Department of Electrical Engineering Institute of Technology Bandung West Java Indonesia Department of Electrical and Computer Engineering University of Manitoba Winnipeg MAN Canada

This paper describes a novel framework in processing speech signals using multifractality concepts, and shows that multifractality could be a new fundamental tool for speech processing. New approaches using the self-similarity model of complexity have been developed to simplify processing of complicated speech signals. The approaches associate signals with fractal sets and then characterize the sets using real numbers called fractal dimensions. This paper extends the approaches by associating speech signals with measures and then characterizing the measures with multifractal curves such as Mandelbrot dimensions (denoted as f(/spl alpha/)) or Renyi dimensions D/sub q/. Such curves (also known as singularity curves) are the characterization of speech signals. This paper shows that multifractal (or singularity) processing of speech is capable of providing important processing aspects: decomposition, representation, and spectrum characterization-a capability that makes Fourier processing of signals is fundamental. The multifractal approach can decompose speech into various segments based on variations of the segment's Holder exponents. The results can be used for new speech segmentation schemes. The multifractal approach is also used in characterizing speech through singularity spectrum. This can be used to develop better accuracy speech recognition schemes. Finally, the paper describes a process to reconstruct speech signals from their singularity representation, by the means of the so-called wavelet maxima.

关键词： Fractals Speech processing Signal processing Speech recognition Laboratories microelectronics Fourier transforms Time measurement Signal design Java

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Operational systems, logistics engineering and technology insertion

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NAVAL ENGINEERS JOURNAL 1997年第3期109卷 205-220页

作者： Grubb, MJ Skolnick, A Michael J. Grubb:has perfomzed naval engineering at the Crane Division Naval Surface Warfare Center (NSWC) for more than twenty-five years. He currently the program manager for the Sustainable Hardware and Affordable Readiness Practice Program (SHARP). is a Navy-wide logistics research and development prgram aimed at the successful transiton of proved technologies inot the fleet. SHARP focuses on reducing acquisition performance capability reliability maintainability and readiness of these systems. Mr. Grubb has served as a department director for the past eleven years. His most recent assignment was as director of the Tactical Computer Resources and Test Equipment Department. This organization provided acquisition and in-service engineering support of the Navy's tectical embedded computers priphirals displays and mass memory storage devices. The organization also provided a complete range of product engineering and metrology engineerig services for SSP NevSeaSysCom and the Trident Program. Prior to this appointment Mr. Grubb was deptuy director psysical security programs department and site responsible for program management and system integration of ashore integrated security systems. Mr. Grubb holds a B.S. degree in industrial engineering from Iowa State Universtiy an M.S. degree in industrial engineering from Purdue University and has copleted the course work (Dec.'96 for a master's degree in public and environment affairs at Indiana University-Purdue Univeristy Indianapolis. Dr. Alfred Skolnick operates System Science Consultants (SSC) specilizing in strategic planning technical program definiton technology assessment and engineering analyses on selected matters of national interest. He has taught physics mathematics and management sciences at University of Virginia and Marymount University and is currently adjunct professor of mathematics at Northern Virginia Community College. Form 1985 to 1989 he was president of the American Society of Noval Engineers. Dr. Skolnick served at Applied Physic

In an era of fiscal austerity, downsizing and unforgiving pressure upon human and economic capital, it is an Augean task to identify resources for fresh and creative work. The realities of the day and the practical demands of more immediate fleet needs can often dictate higher priorities. Yet, the Navy must avoid eating its seed corn. Exercising both technical insight and management foresight, the fleet, the R&D community, the Office of the Chief of Naval Operations (OpNav) and the product engineering expertise of the Naval Surface Warfare Center (NSWC) are joined and underway with integrated efforts to marry new, fully demonstrated technologies and operational urgencies. Defense funding today cannot sponsor all work that can be mission-justified over the long term because budgets are insufficient to support product maturation within the classical development cycle. However, by rigorous technical filtering and astute engineering of both marketplace capabilities and currently available components, it is possible in a few select cases to compress and, in effect, integrate advanced development (6.3), engineering development (6.4), weapon procurement (WPN), ship construction (SCN), operation and maintenance (O&M,N) budgetary categories when fleet criticalities and technology opportunities can happily meet. In short, 6.3 funds can be applied directly to ''ripe gateways'' so modern technology is inserted into existing troubled or aging systems, sidestepping the lengthy, traditional development cycle and accelerating practical payoffs to recurrent fleet problems. To produce such constructive results has required a remarkable convergence of sponsor prescience and engineering workforce excellence. The paper describes, extensively, the philosophy of approach, transition strategy, polling of fleet needs, technology assessment, and management team requirements. The process for culling and selecting specific candidate tasks for SHARP sponsorship (matching operational need with t

关键词： Naval vessels

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An improved ASIC design and implementation for color space conversion applications

An improved ASIC design and implementation for color space c...

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Midwest Symposium on Circuits and systems (MWSCAS)

作者： M. Nsour H.S. Abdel-Aty-Zohdy Microelectronics System Design Laboratory Department of Electrical and Systems Engineering Oakland University Rochester MI USA

The design and VLSI implementation of an ASIC chip, which performs real time conversion, the Red, Green, and Blue (RGB) color coordinates to CIE (Commission Internationale de l'Eclairage) standard L* (luminance), a* (redness-greenness), and b* (yellowness-blueness) color coordinates, is presented. High-speed operation of this ASIC is achieved by pipelining the input data, and performing parallel operations. The ASIC is implemented using CMOS, 2.0 /spl mu/m, n-well process. It occupies an area of 1.55/spl times/1.45 mm/sup 2/. The chip is intended to be used in colorimetry manufacturing inspection and robotics precision. Inputs are 3 bits each. a* and b* are 7 bits each, L* is 6 bits.

关键词： Application specific integrated circuits systems engineering and theory Inspection Application software Humans Extraterrestrial measurements Instruments Color microelectronics Laboratories

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Uncertain nonlinear algebraic solutions and their implementation using neural networks

Uncertain nonlinear algebraic solutions and their implementa...

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Midwest Symposium on Circuits and systems (MWSCAS)

作者： H.S. Abdel-Aty-Zohdy M.A. Zohdy M. Karam Microelectronics System Design Lab Department of Electrical and Systems Engineering Oakland University Rochester MI USA Department of Electrical and Systems Engineering Oakland University Rochester MI USA

In this article, we propose a dynamic recurrent approach to solve uncertain nonlinear algebraic equations. The approach is justified on the basis of net construction that recursively produces minimum neuron state energy which corresponds to the desired solution. Linearization via the Newton-Raphson method is employed in order to make the net converge to an appropriate region in the solution space. Some preliminary experimentation on non-trivial nonlinear examples are included and discussed. Approaches for hardware implementation of the recurrent dynamic neural network are presented. Comparison between a totally digital chip design and a hybrid analog/digital implementation utilizing MOSIS facilities is made. Evaluation and simulations on system, logic, and circuit levels are emphasized.

关键词： Nonlinear equations Neurons Newton method Neural network hardware Nonlinear dynamical systems Neural networks Recurrent neural networks Chip scale packaging Circuit simulation Logic circuits

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Combinational logic approach for designing RNS multipliers

Combinational logic approach for designing RNS multipliers

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Midwest Symposium on Circuits and systems (MWSCAS)

作者： A.A. Hiasat H. Abdel-Aty-Zohdy Electronics Engineering Department Royal Scientific Society Princess Sumaya University for Technology Amman Jordan Microelectronics System Desigh Laboratory Electrical and Systems Engineering Oakland University Rochester MI USA

The design of Residue Number system (RNS) multipliers has received considerable attention in the last few years. This paper presents a new approach for designing modular multipliers using a combinational logic technique. The idea is based on constructing a truth table whose inputs are the bits of the multiplicand and the multiplier. The outputs are the bits of the modular product. Realizing any minimized Boolean function is achieved using two levels of gates. Compared to most recent developed approach, our new technique requires less integrated circuit area and operates at a higher speed.

关键词： Minimization methods Zinc

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Affordability, logistics R&D and fleet systems

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NAVAL ENGINEERS JOURNAL 1996年第3期108卷 199-213页

作者： Schulte, DP Skolnick, A He has supported the development and operation of several naval systems including advanced component selection for Trident II fire control and navigation systems. He served as branch manager of the Surface Ship ASW Combat System Branch which acted as the acquisition engineering agent for the AN/SQQ-89 Surface Ship Anti-Submarine Warfare Weapon System. He was then selected to manage the Module Engineering Department which provided engineering support to numerous naval systems including the AN/BSY-1 Submarine Combat System and the Trident II fire control and navigation system. He then served as the deputy program manager for NAVSEA Progressive Maintenance (2M/ATE). He holds a B.S. degree in Electrical Engineering from Purdue University and currently is pursuing a Maste's degree in Public Environmental Affairs at Indiana University—Purdue University Indianapolis. He served at Applied Physics Laboratory/The Johns Hopkins University in missile development then aboard USS Boston (CAG-1) and played leading roles in several weapon system developments (Regulus Terrier Tartar Talos) inertial navigation (Polaris) deep submergence (DSRV) and advanced ship designs (SES). He later was director Combat System Integration Naval Sea Systems Command and head Combat Projects Naval Ship Engineering Center. He led the Navy's High Energy Lasers and Directed Energy Weapons development efforts. He was vice president advanced technology at Operations Research Inc. and vice president maritime engineering at Defense Group Inc. before starting SSC in 1991. Dr. Skolnick holds a B.S. degree in Mathematics and Economics Queens College an M.A. degree in Mathematics and Philosophy Columbia University an M.S. degree in Electrical/Aeronautical Engineering U.S. Naval Postgraduate School and a Ph.D. in Electrical Engineering and Applied Mathematics from Polytechnic University in New York. He is the author of many published papers on engineering design issues source selection procedures and large-scale complex technology problems

The Fleet continues to require high performance systems that can operate with dependability in the seas' unforgiving environments and under hostile action. Those demands are not new. What has changed is the urgent priority formerly assigned to national defense issues. The arguments for continued superpower military strength are now roiled in politics along with unsettled budgets and uncertain force level projections. Current expectations revolve about indefinite fiscal and operational issues (difficult funding constraints and broadband threats). In the actual event of ''doing more with less,'' a practical response is to apply the creative power available from sound engineering judgement and the crucible of experience to the immediate needs of the Fleet. The attempt to shorten the path between advanced development effort and Fleet use has been tried occasionally in the past, often, without exemplary results. The Sustainable Hardware and Affordable Readiness Practices (SHARP) program, is a generic R&D effort under OpNav sponsorship that has been working steadily on sensible solutions to product engineering problems. Armed today with fast-time, large-scale computation abilities and modern tools for technical problem solving coupled with specialized engineering knowledge, it has been refreshed and is underway satisfying existing Fleet needs. The relationship between fully responsive engineering services and current operational needs is always demanding. The connection between advanced engineering development (6.3 category funds) and immediate Fleet usage brings added complexity and challenge, both technical and organizational. Illustrative examples of affordable engineering solutions to ''retain, revise, replace or retire'' questions are presented within the context of both Fleet realities and budgetary limitations. The discussion covers legacy system support, civil/military considerations and Fleet maintenance issues. It describes the substantial and critical payoffs i

关键词： Warships

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An algorithm for the design of a residue-to-binary converter

An algorithm for the design of a residue-to-binary converter

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Midwest Symposium on Circuits and systems (MWSCAS)

作者： A.A. Hiasat H.S. Abdel-Aty-Zohdy Microelectronics System Design Laboratory Department of Electrical and Systems Engineering Oakland University Rochester MI USA

This paper presents a new algorithm which converts moduli (2/sup k/, 2/sup k/-1, 2/sup k/-1-1) residue numbers to their binary equivalents. A suitable hardware implementation which utilizes binary adders, and needing no memory, is proposed. If the system is pipelined, then the throughput rate is that of a single (3k-1) bits adder. Thus, hardware requirements and execution time are less, with corresponding larger dynamic range.

关键词： Algorithm design and analysis Signal processing algorithms Hardware Equations microelectronics Laboratories design engineering systems engineering and theory Throughput Adders

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A high-speed division algorithm for residue number system

A high-speed division algorithm for residue number system

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IEEE International Symposium on Circuits and systems (ISCAS)

作者： A.A. Hiasat H.S. Abdel-Aty-Zohdy Microelectronics System Design Laboratory Department of Electrical and Systems Engineering Oakland University Rochester MI USA

A new algorithm for one of the longstanding problems in residue number system, namely division, is presented. The algorithm is very simple. It approaches the paper-and-pencil division procedure where the quotient is selected to guarantee a non-negative remainder. This algorithm does not require sign and overflow detection, scaling, or redundant moduli. Based on computer simulation results, the algorithm is four times faster than the most recent and competitive published work by Lu and Chiang (see IEEE Trans. Compu., vol. C-41, no. 8, p. 1026-32, 1992).

关键词： Hardware Cathode ray tubes microelectronics Laboratories design engineering systems engineering and theory Computer simulation Digital arithmetic Dynamic range Decoding

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Neural networks for pattern discovery and optimization in signal processing and applications

Neural networks for pattern discovery and optimization in si...

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Canadian Conference on electrical and Computer engineering (CCECE)

作者： H.S. Abdel-Aty-Zohdy M.A. Zondy Microelectronics System Design Laboratory Electrical and Systems Engineering Oakland University Rochester MI USA Center for Advanced Automation Electrical and Systems Engineering Oakland University Rochester MI USA

The article is intended to advance both conceptual and implementation techniques of supervised and discovery-driven neural networks in noisy time varying signal processing applications. Successful neural networks and their significance in applications are based on; selection of proper theoretical algorithms for learning, appropriate selection of the sequencing of signal processing tasks, and efficient VLSI system implementation. We present a pattern discovery self organizing feature map (SOFM), followed by a recurrent dynamic neural network (RDNN) algorithm for signal representation and processing. This approach combines the benefits of RDNNs with its SOFM counter part. Preliminary designs, implementations, test results and validation of silicon-chips for each of the above neural network approach are also presented.

关键词： Neural networks Intelligent networks Signal processing Signal processing algorithms Multidimensional signal processing Organizing systems engineering and theory Very large scale integration Recurrent neural networks Stochastic processes

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