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检索条件"机构=Microelectronics System Design Laboratory Electrical and Systems Engineering"

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Reinforcement neural learning with application to gas sensors

Reinforcement neural learning with application to gas sensor...

引用

Midwest Symposium on Circuits and systems (MWSCAS)

作者： H.S. Abdel-Aty-Zohdy Microelectronics System Design Laboratory Department of Electrical and Systems Engineering Oakland University Rochester MI USA

Neural net reinforcement learning algorithm and its application to gas (chemicals) classification and quantification are considered in this paper. The approach does not require memory and has simplified reward/punishment computations. The advantages and disadvantages of the reinforcement algorithm are contrasted against other competing neural algorithms. The reinforcement learning has been found practical, when each gas (chemical) is distinguished by several features and characteristics with possible overlap. The paper also gives an account of integrated circuit digital chip implementation for typical four gases with temperature, pressure, and flow quantity features. The number of required iterations has been found to depend on reward and penalty parameters, as well as the threshold governing the learning. It is believed that our implementation approach has potential uses in auto industry safety and emission control, as well in automated semiconductor manufacturing process.

关键词： Gas detectors Learning Chemicals Neural networks Digital integrated circuits Gases Temperature Industrial control Manufacturing industries Safety

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Reinforcement learning neural network circuits for electronic nose

Reinforcement learning neural network circuits for electroni...

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IEEE International Symposium on Circuits and systems (ISCAS)

作者： H.S. Abdel-Aty-Zohdy M. Al-Nsour Microelectronics System Design Laboratory Department of Electrical and Systems Engineering Oakland University Rochester MI USA

This paper approaches electronic nose design from two promising angles: reinforcement neural network (RNN) learning algorithms, and naturally compatible analog circuits. This approach is inspired by biological sensing and discrimination of a multitude of odors in a background environment. A VLSI system approach is presented for classification of chemical compounds, with knowledge of key features only. Based on utilizing microsensor arrays, reinforcement neural networks are used to affect nonparametric pattern recognition, classification, and distinction among multicomponent chemicals. A specialized RNN approach is chosen. Realization and implementation of analog RNN circuits is presented using 1.2 /spl mu/m CMOS n-well technology, at AMI, through the MOSIS facilities. Preliminary results are satisfactory and lend evidence to the effectiveness of the analog designed neural network building blocks for temporal and spatial NN pattern recognition.

关键词： Learning Neural networks Electronic noses Recurrent neural networks Pattern recognition CMOS technology Algorithm design and analysis Analog circuits Very large scale integration Chemical compounds

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An improved ASIC design and implementation for color space conversion applications

An improved ASIC design and implementation for color space c...

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Midwest Symposium on Circuits and systems (MWSCAS)

作者： M. Nsour H.S. Abdel-Aty-Zohdy Microelectronics System Design Laboratory Department of Electrical and Systems Engineering Oakland University Rochester MI USA

The design and VLSI implementation of an ASIC chip, which performs real time conversion, the Red, Green, and Blue (RGB) color coordinates to CIE (Commission Internationale de l'Eclairage) standard L* (luminance), a* (redness-greenness), and b* (yellowness-blueness) color coordinates, is presented. High-speed operation of this ASIC is achieved by pipelining the input data, and performing parallel operations. The ASIC is implemented using CMOS, 2.0 /spl mu/m, n-well process. It occupies an area of 1.55/spl times/1.45 mm/sup 2/. The chip is intended to be used in colorimetry manufacturing inspection and robotics precision. Inputs are 3 bits each. a* and b* are 7 bits each, L* is 6 bits.

关键词： Application specific integrated circuits systems engineering and theory Inspection Application software Humans Extraterrestrial measurements Instruments Color microelectronics Laboratories

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An algorithm for the design of a residue-to-binary converter

An algorithm for the design of a residue-to-binary converter

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Midwest Symposium on Circuits and systems (MWSCAS)

作者： A.A. Hiasat H.S. Abdel-Aty-Zohdy Microelectronics System Design Laboratory Department of Electrical and Systems Engineering Oakland University Rochester MI USA

This paper presents a new algorithm which converts moduli (2/sup k/, 2/sup k/-1, 2/sup k/-1-1) residue numbers to their binary equivalents. A suitable hardware implementation which utilizes binary adders, and needing no memory, is proposed. If the system is pipelined, then the throughput rate is that of a single (3k-1) bits adder. Thus, hardware requirements and execution time are less, with corresponding larger dynamic range.

关键词： Algorithm design and analysis Signal processing algorithms Hardware Equations microelectronics Laboratories design engineering systems engineering and theory Throughput Adders

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Formal verification and performance evaluation of logic integrated systems based on hierarchical analysis

Formal verification and performance evaluation of logic inte...

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Midwest Symposium on Circuits and systems (MWSCAS)

作者： F.A. El-Licy H.S. Abdel-Aty-Zohdy Microelectronics System Design Laboratory Department of Electrical and Systems Engineering Oakland University Rochester MI USA

ISBN: (纸本)078037150X

Formal verification of very large scale integrated circuit (VLSIC) involves the formal correctness of the functionality of a given design, while circuit validation involves the reliability and efficiency of the design. A hierarchical approach for computation, of IC design efficiency is proposed and implemented using figures of merit. The work has been motivated to partially complete an IC formal verification tool. The implemented system is integrated into a formal verification environment to reflect the performance of the verified system. The system is capable of analyzing the power dissipation and figures of merit using equivalent R and C components. The hierarchical analysis and evaluation of figures of merit general factors obtained at different system levels represent performance evaluation of each gate. An illustrative example of a 6/spl times/6 carry look-ahead adder is given and worst case conditions have been determined. The system performance may thus be improved.

关键词： Formal verification CMOS logic circuits Binary trees Power dissipation Semiconductor device modeling Laboratories Performance analysis Switches Delay effects Logic design

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A high-speed division algorithm for residue number system

A high-speed division algorithm for residue number system

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IEEE International Symposium on Circuits and systems (ISCAS)

作者： A.A. Hiasat H.S. Abdel-Aty-Zohdy Microelectronics System Design Laboratory Department of Electrical and Systems Engineering Oakland University Rochester MI USA

A new algorithm for one of the longstanding problems in residue number system, namely division, is presented. The algorithm is very simple. It approaches the paper-and-pencil division procedure where the quotient is selected to guarantee a non-negative remainder. This algorithm does not require sign and overflow detection, scaling, or redundant moduli. Based on computer simulation results, the algorithm is four times faster than the most recent and competitive published work by Lu and Chiang (see IEEE Trans. Compu., vol. C-41, no. 8, p. 1026-32, 1992).

关键词： Hardware Cathode ray tubes microelectronics Laboratories design engineering systems engineering and theory Computer simulation Digital arithmetic Dynamic range Decoding

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DMQ: Dual-Mode Q-Learning Hardware Accelerator for Shortest Path and Coverage Area 37

DMQ: Dual-Mode Q-Learning Hardware Accelerator for Shortest ...

引用

37th IEEE International system-on-Chip Conference, SOCC 2024

作者： Syafalni, Infall Firdaus, Mohamad Imam Sutisna, Nana Adiono, Trio Juhana, Tutun Mulyawan, Rahmat Bandung Institute of Technology School of Electrical Engineering and Informatics Indonesia University Center of Excellence on Microelectronics Bandung Institute of Technology Indonesia The University of Tokyo System Design Laboratory School of Engineering Tokyo Japan

ISBN: (纸本)9798350377569

In this paper, we propose a novel dual-mode Q-learning hardware accelerator (DMQ) for shortest path and coverage area problems. The hardware accelerator design uses only an agent to tackle multiple modes, in this case, shortest path and coverage area problems for mobile robots. The work proposes a modified policy generator that supports two reward functions for the shortest path and coverage area. The coverage area mode has 4 × state spaces than that of the shortest path mode. We also explore some policy generators such as decreasing epsilon and greedy for the dual-mode Q-learning accelerator. Experimental results show that by using a greedy policy generator the learning rate of an agent is faster for both problems. Moreover, the hardware architecture requires only 1199 LUTs, 4 LUTRAMs, and 6 BRAMs for the dual-mode functions. With a throughput of 185.63 MHz, the proposed work outperforms other methods up to 13 × in energy efficiency. The proposed work is useful for disaster recovery, smart navigation, and other artificial intelligence applications. © 2024 IEEE.

关键词： Mobile robots

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A genetic algorithm tracking model for product deployment in telecom services

A genetic algorithm tracking model for product deployment in...

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2005 IEEE International 48th Midwest Symposium on Circuits and systems, MWSCAS 2005

作者： Murphy, Linda Abdel-Aty-Zohdy, Hoda S. Hashem-Sherif, M. Microelectronics System Design Laboratory Oakland University Electrical and Systems Engineering Rochester MI United States AT and T Bell Labs. C5-2018 200 S. Laurel Avenue Middletown NJ United States

ISBN: (纸本)0780391977

Genetic algorithms (GA) are designed to search for, discover and emphasize good solutions by applying selection and crossover techniques, inspired by nature, to supply solutions to engineering systems. Genetic algorithms operate on pieces of information like nature does on genes in the course of evolution. All individuals of one generation are evaluated by a fitness function. This paper presents an approach to implement a genetic algorithm to depict a recently developed "Integrated Model" for defect tracking for product deployment in telecommunication systems by means of a solution space representing target variables. The genetic algorithm inputs these target values as dynamic input measurements. From these measurements, the best possible fused values are found for the target variables. The goal of the genetic algorithm is dynamically to update the parameters applied to the input measurements to find the optimum solution for the defect tracking model system. Focus will be given to one dimension of sensor input measurements consisting of three four-bit binary sensor inputs varying within a given range of data points. The genetic algorithm is applied to these inputs by means of a 64 6-bit random member binary population using the "Half-Sibling and a Clone" (HSAC) technique of crossover and mutation. The population members are evaluated using a fitness function where the fittest individuals are retained to survive and produce offspring for the next generation and the remainder are discarded. Genetic diversity is maintained through using a roulette wheel technique. The simulation tool MATLAB will be used to simulate the genetic algorithm. The genetic algorithm will be completed in VLSI using Verilog and the Mentor Graphics tools. The first stage components have been designed and completed using the Mentor Graphics tool-set. © 2005 IEEE.

关键词： Genetic algorithms

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Analog multiplexing in time domain for biochemical measurement processing

Analog multiplexing in time domain for biochemical measureme...

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Midwest Symposium on Circuits and systems (MWSCAS)

作者： A. Patel T. Terry H.S. Abdel-Aty-Zohdy Microelectronics System Design Laboratory (MSDL) Electrical and Systems Engineering Department Oakland University Rochester MI USA

Digital Multiplexers and Analog multiplexers, through the use of filters and their applications implemented in frequency domain, which requires extensive hardware and is costly have seen substantial amount of research compared to an analog multiplexer in time domain. This Paper Presents design, Simulation, Implementation and Evaluation of a four-to-one analog multiplexer. The analog multiplexer is implemented with the help of four buffers and four transmission gates using 0.35 /spl mu/m CMOS Technology with optimum linear ranges that covers 60% of total input supply voltage. The analog multiplexer is developed for a biochemical preprocessing unit to multiplex time-varying analog input signals coming from real-time sensor arrays and to connect the selected input to one A/D converter for digital implementation of a bio-inspired intelligent signal detection system or to an analog implemented biochemical detection system.

关键词： Time measurement Multiplexing Sensor arrays CMOS technology Intelligent sensors Digital filters Frequency domain analysis Hardware Voltage Data preprocessing

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A wide input range analog multiplier for neuro-computing

A wide input range analog multiplier for neuro-computing

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Midwest Symposium on Circuits and systems (MWSCAS)

作者： M. Al-Nsour H.S. Abdel-Aty-Zohdy Microelectronics Systems Design Laboratory Department of Electrical and Systems Engineering Oakland University Rochester MN USA Microelectronics Systems Design Laboratory Department of Electrical and Systems Engineering Oakland University Rochester MI USA

A wide input range 4-quadrant analog multiplier design and its VLSI implementation are presented. The design is based on the squaring law operation of saturated NMOS transistors. The circuit is realized by using 12 NMOS and 2 PMOS transistors. The multiplier accepts two signed inputs in the range of /spl plusmn/4 V. The simulated corner frequency is found to be at 85 MHz. N-well 2 /spl mu/m CMOS double metal process is utilized. It occupies 99/spl times/160 /spl mu/m/sup 2/. Statistical linear regression showed that the multiplier has less than 1% overall error. By extending the input range and minimizing the silicon area, this design has high potential in evolving neuro-computing applications.

关键词： MOSFETs Silicon Neural networks Neurons Intrusion detection Threshold voltage Circuit analysis design optimization microelectronics Laboratories

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