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IEEE International Symposium on Circuits and systems (ISCAS)

作者： A.A. Hiasat H.S. Abdel-Aty-Zohdy Microelectronics System Design Laboratory Department of Electrical and Systems Engineering Oakland University Rochester MI USA

A new algorithm for one of the longstanding problems in residue number system, namely division, is presented. The algorithm is very simple. It approaches the paper-and-pencil division procedure where the quotient is selected to guarantee a non-negative remainder. This algorithm does not require sign and overflow detection, scaling, or redundant moduli. Based on computer simulation results, the algorithm is four times faster than the most recent and competitive published work by Lu and Chiang (see IEEE Trans. Compu., vol. C-41, no. 8, p. 1026-32, 1992).

关键词： Hardware Cathode ray tubes microelectronics Laboratories design engineering systems engineering and theory Computer simulation Digital arithmetic Dynamic range Decoding

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Neural networks for pattern discovery and optimization in signal processing and applications

Neural networks for pattern discovery and optimization in si...

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Canadian Conference on electrical and Computer engineering (CCECE)

作者： H.S. Abdel-Aty-Zohdy M.A. Zondy Microelectronics System Design Laboratory Electrical and Systems Engineering Oakland University Rochester MI USA Center for Advanced Automation Electrical and Systems Engineering Oakland University Rochester MI USA

The article is intended to advance both conceptual and implementation techniques of supervised and discovery-driven neural networks in noisy time varying signal processing applications. Successful neural networks and their significance in applications are based on; selection of proper theoretical algorithms for learning, appropriate selection of the sequencing of signal processing tasks, and efficient VLSI system implementation. We present a pattern discovery self organizing feature map (SOFM), followed by a recurrent dynamic neural network (RDNN) algorithm for signal representation and processing. This approach combines the benefits of RDNNs with its SOFM counter part. Preliminary designs, implementations, test results and validation of silicon-chips for each of the above neural network approach are also presented.

关键词： Neural networks Intelligent networks Signal processing Signal processing algorithms Multidimensional signal processing Organizing systems engineering and theory Very large scale integration Recurrent neural networks Stochastic processes

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Analog signal-selector circuit for quick gas detection from gas-sensor arrays

Analog signal-selector circuit for quick gas detection from ...

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Midwest Symposium on Circuits and systems (MWSCAS)

作者： H.S. Abdel-Aty-Zohdy F.A. El-Licy Dept. of Electr. & Syst. Eng. Oakland Univ. Rochester MI USA Microelectronics System Design Laboratory Department of Electrical and Systems Engineering Oakland University Rochester MI USA

A Sixteen Input Maximum/Minimum Analog signal-selector Circuit (SIMMAC) is designed, simulated, and implemented using 2 /spl mu/m p-well (Orbit) CMOS technology. The circuit is useful in recognition of gas types from measurements of thin-film gas-sensor arrays. The output signal of each thin-film gas detector is typically a function of bias voltages, temperature and pressure, film type, frequency, and gas type. Gas sensor arrays provide profiles of resistivity vs. temperature, for a particular PPM, and/or profiles of resistivity vs. pressure at a particular temperature. Since different chemical gas types have peak resistivity values at a certain temperature and a certain pressure, a selector circuit is needed to identify chemical gas components. The SIMMAC design is based on a multiple-input current comparator median circuit. Simulation results gave an accuracy of better than 94% with analog input signal values from 1.6 to 3.6 V. The SIMMAC is suitable for gas detection from a sensor-array of up to 16-elements with known models and negligible signal distortion. Further, it may be used as a post processor to select the winning synapse in an unsupervised neural network for pattern recognition with distorted and unidentified models of gas mixtures.

关键词： Temperature sensors Conductivity Circuit simulation CMOS technology Thin film circuits Gas detectors Sensor arrays Chemicals Signal design CMOS analog integrated circuits

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design and implementation of a fast and compact residue-based semi-custom VLSI arithmetic chip

Design and implementation of a fast and compact residue-base...

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Midwest Symposium on Circuits and systems (MWSCAS)

作者： A.A. Hiasat H.S. Abdel-Aty-Zohdy Department of Electrical and Systems Engineering Microelectronics Systems Design Laboratory Oakland University Rochester MI USA

design and implementation of a residue-based adder/subtractor/multiplier arithmetic TinyChip for the moduli set (2/sup n/-1,2/sup n/,2/sup n/+1) is addressed in this paper. The unit realization adopts CMOS semi-custom VLSI design, using Octtools-5.0 with the standard cell MSU2-3 library. The implemented chip has the advantage of reduced delay time and hardware requirements. Thus, it can support real-time one and two dimensional signal processing applications. The design does not have dynamic range limitations due to the absence of memory, therefore, this implementation can be expanded for better reliability. Performance of the system is estimated to be 18 million residue arithmetic operations per second on 2 /spl mu/m process.

关键词： Very large scale integration Arithmetic Signal processing algorithms Dynamic range Libraries Hardware Signal processing Logic Algorithm design and analysis microelectronics

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ARCHITECTURE AND NETWORKING ISSUES IN SATELLITE systems FOR PERSONAL COMMUNICATIONS

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INTERNATIONAL JOURNAL OF SATELLITE COMMUNICATIONS 1994年第1期12卷 33-44页

作者： ANANASSO, F CAROSI, M Received the Electronics and Electrical Communications Degree from the University of Rome in 1973 after which he joined Selenia S.p.A (Rome) as a microwave designer in the Development Laboratory. He was involved in several military and civilian projects concerning microwave subsystems for Radar Avionics and Satellite Communications equipment. In 1981 he joined Telespazio S.p.A. (Rome) as Section Chief in the Space and Advanced Programs Division with responsibilities related to satellite payload and digital transmission channel design. In 1987 he was appointed Associate Professor of Digital Signal Processing at the University of Rome Tor Vergata Electronics Engineering Department. In 1990 he again joined Telespazio where he is now Director of the Advanced Studies and Experimentations Division. He has performed a number of studies for National and International Organizations including ESA EUTELSAT INMARSAT and INTELSAT is author of a Radio Systems book a Chapter (‘Digital transmission channel’) of the ‘Satellite Communication System Design’ book by Plenum Publishing (1993) and over 80 technical papers on communication systems and technology. Received the Electronics and Electrical Communications Degree from the University ‘La Sapienza’ of Rome Italy in 1987. From 1987 to 1990 he worked as a Research Engineer in the INFOCOM department of the University ‘La Sapienza’ of Rome carrying out research on design and performance evaluation of multiple access protocols particularly in the metropolitan area network and in the satellite fields. Since 1990 he has been working in the System Studies and Payload group of Telespazio S.p.A. Rome Italy. He is currently involved in projects sponsored by the European Space Agency and by INMARSAT for communications systems via satellite for mobiles both at study and R&D level. Mr Carosi is a member of the IEEE Communication Society.

The paper expands on some specific aspects of personal communications via satellite, often-although not necessarily-envisaging extensive use of 'small' satellites, using orbits not necessarily coinciding with the geostationary one (36,000 km), but rather at 1000-11,000 km altitude. One key point to be borne in mind is the issue of internetworking between satellite and terrestrial systems. Network integration should be carefully implemented in order to comply with ITU future public land mobile telecommunication systems (FPLMTS) requirements, also accepted in the European Telecommunication Standards Institute (ETSI) universal mobile telecommunication systems (UMTS). In addition to some insight into the technology of small satellites and associated orbits, architectures and networking aspects of most relevant systems providing personal communication services (PCS) are addressed in some detail, and potential applications highlighted. Frequency spectrum allocation is addressed in the light of the 1992 World Administrative Radio Conference (WARC-92), taking into account also multiple access problems and regulatory issues such as Federal Communications Commission (FCC) licensing and spectrum sharing debates. Some remarks on critical technologies and cost conclude the paper.

关键词： PERSONAL COMMUNICATIONS SMALL SATELLITES NETWORKING FREQUENCY SPECTRUM

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HYBRID SATELLITE AND TERRESTRIAL NETWORKS

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INTERNATIONAL JOURNAL OF SATELLITE COMMUNICATIONS 1994年第3期12卷 313-327页

作者： CHITRE, DM SHYY, DJ EPHREMIDES, A GUPTA, S COMSAT Laboratories 22300 Comsat Drive Clarksburg MD 20871–9475 USA. Received his B.Sc. from the University of Bombay India an M.A. in mathematics from the University of Cambridge U.K. and a Ph.D. in physics from the University of Maryland. He is currently an Associate Executive Director of the Network Technology Division at COMSAT Laboratories. He has been involved in research and development activities in ISDN VSAT networks data communications and network systems and architectures. Prior to his current positions Dr. Chitre was a Principal Scientist in the Network Technology Division at COMSAT Laboratories. Dr. Chitre joined COMSAT Laboratories in 1980. He has made major contributions to the analysis and architecture of data communication ISDN and BISDN via satellite. Dr. Chitre directs and participates in the international and national standards activities in ISDN BISDN and data communication as they apply to satellite communication. He was Chairman of the Working Group on Protocols and Network Timing Function of the CCIR/CCITT Joint Ad Hoc Group on ISDN/Satellite Matters during 1990–1992. Currently he is the Chairman of the Working Group on New Technologies in the ITU Intersector Coordinating Group (ICG) on Satellite Matters. Dr. Chitre was a programme manager during 1990 and 1991 on a contract from INTELSAT on systems studies on satellite communications systems architectures for ISDN and broadband ISDN systems. Currently he is the technical manager of the DoD Contract on ATM via satellite demonstration and the programme manager for the INTELSAT contract on analysis and top-level specification of INTELSAT ISDN subnetworks and SDH compatible transport network. Received the B.S. degree in electrical engineering from national Chiao-Tung University Hsin-Chu Taiwan in 1983 and the M.S. and Ph.D. degrees in electrical engineering from Georgia Institute of Technology Atlanta GA in 1986 and 1990 respectively. From June 1987 to October 1987 he worked for the Department of Neurology Emory Univers

The role of satellite communications in networks that provide new services, such as frame relay and multimedia, is investigated. Both passive and active (on-board switching/processing) satellite systems are considered. Novel techniques are developed for each system to demonstrate, via detailed analysis and simulation, how the communications bandwidth agility of multipoint/broadcast satellite channels, and the on-board switching/processing, makes it feasible to provide these new services via hybrid satellite and terrestrial networks in a resource-efficient manner.

关键词： HYBRID NETWORKS ON-BOARD PROCESSING FRAME RELAY

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PROCESS-DEPENDENT CIRCUIT MODELING AND SIMULATION OF SOIJFETS - DIGITAL VLSI APPLICATIONS

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SIMULATION 1993年第2期60卷 113-126页

作者： ABDELATYZOHDY, HS TALKHAN, IE [o_1]Microelectronics Systems Design Laboratory Department of Electrical and Systems Engineering Oakland University Rochester Michigan 48309-4401 [o_2]Microelectronics Systems Design Laboratory Department of Electrical and Systems Engineering Oakland University Rochester Michigan 48309-4401

Accurate circuit modeling and simulation of Silicon-on-Insulator (SOI) enhancement and depletion Junction Field-Effect transistors (JFETs) is presented. The nonuniformity in FET device parameters along the channel depth (due to fabrication processes), is taken into account. This is typical in SOI and other thin-film structures. Since SOI fabrication processes parameters are represented, in our model, by a closed form nobility variation, improved model accuracy is guaranteed. Simulation results are found to be within less than 3% of actual measurements. Small-signal circuit-model parameters are determined for SOI FJETs and then evaluated for further logic applications. Inverters with a channel Enhancement-JFET (E-JFET) drivers and n-channel depletion-JFET loads (E/D inverters) are also considered with different supply voltage values, device parameters and digital applications.

关键词： PROCESS-DEPENDENT CIRCUIT MODELING AND SIMULATION THIN FILM SILICON-ON INSULATOR JUNCTION FIELD EFFECT TRANSISTORS VLSI LOGIC CIRCUITS ENHANCEMENT-JFETS

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VLSI implementation of a feature mapping neural network

VLSI implementation of a feature mapping neural network

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Midwest Symposium on Circuits and systems (MWSCAS)

作者： E.T. Carlen H.S. Abdel-Aty-Zohdy Microelectronics Systems Design Laboratory Department of Electrical and Systems Engineering Oakland University Rochester MI USA

Modification of Kohonen's self-organizing feature map algorithm and its dedicated parallel hardware implementation are the focus of this paper. This work is motivated by the need to implement a 5/spl times/5 neural network using digital standard cells and high level VLSI system design tools. The neural net considered is a two layered, feed forward architecture that learns relationships among unknown input data patterns. The prototype system consists of 25 processing units (neurons). Each processing unit operates at 10 MHz. Communication among processing units is accomplished using a broadcast bus. Performance of the system is estimated to be 110,000 iterations per second.< >

关键词： Very large scale integration Neural networks Unsupervised learning Image coding Computer architecture microelectronics Laboratories design engineering systems engineering and theory Focusing

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ZONAL electrical DISTRIBUTION-systems - AN AFFORDABLE ARCHITECTURE FOR THE FUTURE

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NAVAL ENGINEERS JOURNAL 1993年第3期105卷 45-51页

作者： PETRY, CR RUMBURG, JW Chester R. Petry:received a B.S. degree in electrical engineering from the University of Kentucky Lexington Kentucky in 1985. Upon graduation he joined the Electrical System Division of the Propulsion and Auxiliaries Systems Department at the Naval Surface Warfare Center (formerly David Taylor Research Center) Annapolis Maryland where he worked on protective system designs for naval surface combatants. Presently he is working in the Advanced Surface Machinery Programs where he is serving as learn leader for the zonal electrical distribution systems design team. He is a member of IEEE and ASNE. Jay W. Rumburg:is currently assistant manager of the Electrical Engineering Department at Gibbs & Cox Inc. Washington Division. During the past 7 years at Cibbs & Cox Inc. Mr. Rumburg has been extensively involved with the DDG-51 electrical power system and feasibility studies for advanced electrical power systems. His previous experience includes a 20-year career at Johns Hopkins Applied Physics Laboratory in which he participated in various projects involving fleet systems and space programs. After leaving the laboratory he worked on commercial marine and oceanographic projects for various clients. He is a member of ASNE and is retired from the Air Force Reserve.

The electrical system of today's U. S. Navy ships was designed for reliability of power to vital loads. The existing radial electrical system architecture has evolved from World War II to an increasingly complex and expensive system as vital loads have grown and become more power quality sensitive for each new class of ships. The maze of normal and alternate cables on modern navy ships is almost impossible to protect and keep functioning during and after a casualty. The Navy is now demanding that future ships be more affordable while maintaining existing performance capabilities. New studies have shown that zonal electrical distribution system architecture provides a construction cost savings while inherently providing more operational flexibility. This paper will discuss cost and weight comparisons of existing conventional electrical distribution systems to proposed zonal distribution systems on DDG-51 and LSD-41 class ships. It will examine the weight impacts and affordability of installing the zonal distribution system on these ships. Further, it will discuss various zonal distribution system architectures, commonality of components with surface ship electrical distribution systems, and propose developments which will enhance future navy and maritime ship construction.

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Efficient test generation for built-in self-test boundary-scan template

Efficient test generation for built-in self-test boundary-sc...

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1991 IEEE VLSI Test Symposium: Chip-to-system Test Concerns for the 90''s, VTEST 1991

作者： Nagvajara, P. Karpovsky, M.G. Levitin, L.B. Dept. of Electr. and Comput. Eng. Drexel Univ. PhiladelphiaPA United States Research Laboratory for Design and Testing of Computer and Communication Systems Department of Electrical Computer and System Engineering Boston University United States

An analysis and design of a pseudorandom pattern generator, (PRPG), based on a linear recurrence, for built-in self-test (BIST) boundary scan design is presented. The authors present for the case when r≥s, a design of an s-stage PRPG capable of producing 2s-1 distinct r-bit patterns within 2s-1 clock pulses independent of the hardware realization of the PRPG. For the case when rr distinct r-bit patterns and the expected number T(N) of distinct patterns given a number N of clock pulses were presented. The proposed theoretical average N(T) was shown to be close to the experimental average values Nex(T). Hence, the value N(T) or T(N) can be used as a benchmark for evaluating the efficiency of a BIST boundary scan test generation. © 1991 IEEE.

关键词： Built-in self test

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