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Midwest Symposium on Circuits and systems (MWSCAS)

作者： A. Patel T. Terry H.S. Abdel-Aty-Zohdy Microelectronics System Design Laboratory (MSDL) Electrical and Systems Engineering Department Oakland University Rochester MI USA

Digital Multiplexers and Analog multiplexers, through the use of filters and their applications implemented in frequency domain, which requires extensive hardware and is costly have seen substantial amount of research compared to an analog multiplexer in time domain. This Paper Presents design, Simulation, Implementation and Evaluation of a four-to-one analog multiplexer. The analog multiplexer is implemented with the help of four buffers and four transmission gates using 0.35 /spl mu/m CMOS Technology with optimum linear ranges that covers 60% of total input supply voltage. The analog multiplexer is developed for a biochemical preprocessing unit to multiplex time-varying analog input signals coming from real-time sensor arrays and to connect the selected input to one A/D converter for digital implementation of a bio-inspired intelligent signal detection system or to an analog implemented biochemical detection system.

关键词： Time measurement Multiplexing Sensor arrays CMOS technology Intelligent sensors Digital filters Frequency domain analysis Hardware Voltage Data preprocessing

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An Energy-Efficient Computing-in-Memory NN Processor With Set-Associate Blockwise Sparsity and Ping-Pong Weight Update

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IEEE Journal of Solid-State Circuits 2024年第5期59卷 1612-1627页

作者： Yue, Jinshan Liu, Yongpan Feng, Xiaoyu He, Yifan Wang, Jingyu Yuan, Zhe Zhan, Mingtao Liu, Jiaxin Su, Jian-Wei Chung, Yen-Lin Wu, Ping-Chun Hong, Li-Yang Chang, Meng-Fan Sun, Nan Dou, Chunmeng Li, Xueqing Liu, Ming Yang, Huazhong Tsinghua University Department of Electronic Engineering Beijing100084 China Chinese Academy of Sciences Institute of Microelectronics Beijing100029 China National Tsing Hua University Department of Electrical Engineering Hsinchu314040 Taiwan Frontier Institute of Chip and System State Key Laboratory of Integrated Chips and Systems Fudan University Shanghai200433 China

Computing-in-memory (CIM) chips have demonstrated the potential high energy efficiency for low-power neural network (NN) processors. Even with energy-efficient CIM macros, the existing system-level CIM chips still lack deep exploration on sparsity and large models, which prevents a higher system energy efficiency. This work presents a CIM NN processor with more sufficient support of sparsity and higher utilization rate. Three key innovations are proposed. First, a set-associate blockwise sparsity strategy is designed, which simultaneously saves execution time, power, and storage space. Second, a ping-pong weight update mechanism is proposed for a higher utilization rate, enabling simultaneous execution of CIM and write operations. Third, an efficient CIM macro is implemented with adaptive analog-digital converter (ADC) precision for better sparsity utilization and performance-accuracy trade-off. The 65-nm fabricated chip shows 9.5-TOPS/W system energy efficiency at 4-bit precision, with 6.25times actual improvement compared with a state-of-the-art CIM chip. Besides, this work supports high CIM execution accuracy on the ImageNet dataset. © 1966-2012 IEEE.

关键词： Neural networks

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A hardware implementation of genetic algorithms for measurement characterization

A hardware implementation of genetic algorithms for measurem...

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IEEE International Conference on Electronics, Circuits and systems (ICECS)

作者： M.S. Sharawi J. Quinlan H.S. Abdel-Aty-Zohdy Microelectronics System Design Laboratory Electrical and Systems Engineering Oakland University Rochester MI USA

To process/store/analyze signals acquired from sensors, hybrid systems with flexible and adaptable intelligent information processing and perception (IIPP) are needed. Genetic algorithms (GA) present a suitable pre-processing operation because of their good convergence to optimum solutions and characterization capabilities. Most GAs are built via software because of their ease of editing and customization. Less attention has been given to hardware implementation of such algorithms. We present a hardware design approach of a GA for optimum measurement representation/characterization to a following IIPP stage. A multilevel verification of the GA is performed via VHDL. In particular the design of efficient universal multipliers and dividers is addressed. A new time efficient approach for crossover based on preassigned least error value is proposed. The crossover scheme is called half siblings and a clone. Such a scheme needs 10 iterations to converge the system proposed for sensor measurement characterization. This takes 7680 clock cycles, which is only 96 /spl mu/sec when implemented in the 0.25 /spl mu/m CMOS technology.

关键词： Hardware Genetic algorithms Intelligent sensors Sensor phenomena and characterization Sensor systems CMOS technology Information analysis Signal analysis Signal processing Information processing

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A wide input range analog multiplier for neuro-computing

A wide input range analog multiplier for neuro-computing

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Midwest Symposium on Circuits and systems (MWSCAS)

作者： M. Al-Nsour H.S. Abdel-Aty-Zohdy Microelectronics Systems Design Laboratory Department of Electrical and Systems Engineering Oakland University Rochester MN USA Microelectronics Systems Design Laboratory Department of Electrical and Systems Engineering Oakland University Rochester MI USA

A wide input range 4-quadrant analog multiplier design and its VLSI implementation are presented. The design is based on the squaring law operation of saturated NMOS transistors. The circuit is realized by using 12 NMOS and 2 PMOS transistors. The multiplier accepts two signed inputs in the range of /spl plusmn/4 V. The simulated corner frequency is found to be at 85 MHz. N-well 2 /spl mu/m CMOS double metal process is utilized. It occupies 99/spl times/160 /spl mu/m/sup 2/. Statistical linear regression showed that the multiplier has less than 1% overall error. By extending the input range and minimizing the silicon area, this design has high potential in evolving neuro-computing applications.

关键词： MOSFETs Silicon Neural networks Neurons Intrusion detection Threshold voltage Circuit analysis design optimization microelectronics Laboratories

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Bio-inspired integrated circuits for signal perception and processing

Bio-inspired integrated circuits for signal perception and p...

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2003 Nanotechnology Conference and Trade Show - Nanotech 2003

作者： Abdel-Aty-Zohdy, Hoda S. Ewing, Robert L. Microelectronics System Design Lab Department of Electrical Engineering Rochester MI 48309 United States Information Directorate Air Force Research Laboratory Wright-Patterson AFB OH 45433 United States

ISBN: (纸本)0972842209

Bio-inspired systems utilizing neural networks (NNs) and genetic algorithms (GAs) are presented for communications, networking information dissemination, and real-time control in signal perception and processing (SPP). VLSI and nano circuits and systems will provide affordable, reproducible, and reliable front-end high performance SPP. Sample applications are presented for integrated intelligent E-Nose systems, and Communication systems which include: i-Self-Organizing feature Map for discovery, ii- Recurrent Dynamic Neural Networks (NNs), with output neurons feedback and feed forward arrays for noisy signals, iii- Reinforcement NNs for applications with only key features, rather than a known model, iv- Spiking NNs that adjust their synapses subject to changes in the environment, and v- Genetic Algorithms for characterization and optimization.

关键词： Integrated circuits

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Dynamic impedance model of piezo ElectroChemical transducer effect for a smart battery

Dynamic impedance model of piezo ElectroChemical transducer ...

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2005 IEEE International 48th Midwest Symposium on Circuits and systems, MWSCAS 2005

作者： Teli, Purvi S. Abdel-Aty-Zohdy, Hoda S. Line Vogel, F. Ewing, Robert L. Microelectronics System Design Laboratory Department of Electrical and System Engineering Oakland University Rochester MI 48309 GraphiTech Inc. St. Clair Shores MI 48080 Air Force Research Laboratory Information Directorate Wright-Patterson AFB OH 45433

ISBN: (纸本)0780391977

Intelligent power management for dry cell batteries may be accomplished by external circuitry which is connected to the individual power cells. In comparison, the presented Graphite circuit model, along with lead-acid battery technology facilitates the power management of wet cells in sealed packaging. This paper reiterates the Piezo ElectroChemical Transducer (PECT) effect based on the intercalation of graphite with sulfuric acid;Introduces a first attempt at developing a dynamic circuit model which will facilitate for a wide range of smart PECT applications. The paper also addresses the usage of PECT effect device for smart battery management, which operates in sulfuric acid environment. The developed dynamic impedance circuit model of PECT effect device can be used further to understand the changes in resistance and reactance properties of PECT device with the change in the temperature, voltage, current, stages, type of graphite and the concentration of sulfuric acid of electrochemical intercalation of graphite with sulfuric acid. © 2005 IEEE.

关键词： Photoelectrochemical cells

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A genetic algorithm tracking model for product deployment in telecom services

A genetic algorithm tracking model for product deployment in...

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2005 IEEE International 48th Midwest Symposium on Circuits and systems, MWSCAS 2005

作者： Murphy, Linda Abdel-Aty-Zohdy, Hoda S. Hashem-Sherif, M. Microelectronics System Design Laboratory Oakland University Electrical and Systems Engineering Rochester MI United States AT and T Bell Labs. C5-2018 200 S. Laurel Avenue Middletown NJ United States

ISBN: (纸本)0780391977

Genetic algorithms (GA) are designed to search for, discover and emphasize good solutions by applying selection and crossover techniques, inspired by nature, to supply solutions to engineering systems. Genetic algorithms operate on pieces of information like nature does on genes in the course of evolution. All individuals of one generation are evaluated by a fitness function. This paper presents an approach to implement a genetic algorithm to depict a recently developed "Integrated Model" for defect tracking for product deployment in telecommunication systems by means of a solution space representing target variables. The genetic algorithm inputs these target values as dynamic input measurements. From these measurements, the best possible fused values are found for the target variables. The goal of the genetic algorithm is dynamically to update the parameters applied to the input measurements to find the optimum solution for the defect tracking model system. Focus will be given to one dimension of sensor input measurements consisting of three four-bit binary sensor inputs varying within a given range of data points. The genetic algorithm is applied to these inputs by means of a 64 6-bit random member binary population using the "Half-Sibling and a Clone" (HSAC) technique of crossover and mutation. The population members are evaluated using a fitness function where the fittest individuals are retained to survive and produce offspring for the next generation and the remainder are discarded. Genetic diversity is maintained through using a roulette wheel technique. The simulation tool MATLAB will be used to simulate the genetic algorithm. The genetic algorithm will be completed in VLSI using Verilog and the Mentor Graphics tools. The first stage components have been designed and completed using the Mentor Graphics tool-set. © 2005 IEEE.

关键词： Genetic algorithms

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Artificial neural network electronic nose for volatile organic compounds

Artificial neural network electronic nose for volatile organ...

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Great Lakes Symposium on VLSI

作者： H.S. Abdel-Aty-Zohdy Microelectronics System Design Lab Department of Electrical and Systems Engineering Oakland University Rochester MI USA

Advanced microsystems that include, sensors, interface-circuits, and pattern-recognition integrated monolithically or in a hybrid module are needed for civilian, military, and space applications. These include: automotive, medical applications, environmental engineering, and manufacturing automation. ASICs with Artificial Neural Networks (ANN) are considered in this paper, with the objective of recognizing air-borne volatile organic compounds, especially alcohols, ethers, esters, halocarbons, NH/sub 3/, NO/sub 2/, and other warfare agent simulants. The ASIC inputs are connected to the outputs from array-distributed sensors which measure three-features for identifying each of four chemicals. A Specialized Reinforcement Neural Network (RNN) learning approach is chosen for the chemicals classification problem. Hardware implementation of the RNN is presented for 2 /spl mu/m CMOS process, MOSIS chip. design implementation and evaluation are also presented.

关键词： Artificial neural networks Electronic noses Sensor arrays Automotive engineering Chemical sensors Recurrent neural networks Medical services Biomedical equipment Biomedical engineering Manufacturing automation

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VLSI implementation of a feature mapping neural network

VLSI implementation of a feature mapping neural network

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Midwest Symposium on Circuits and systems (MWSCAS)

作者： E.T. Carlen H.S. Abdel-Aty-Zohdy Microelectronics Systems Design Laboratory Department of Electrical and Systems Engineering Oakland University Rochester MI USA

Modification of Kohonen's self-organizing feature map algorithm and its dedicated parallel hardware implementation are the focus of this paper. This work is motivated by the need to implement a 5/spl times/5 neural network using digital standard cells and high level VLSI system design tools. The neural net considered is a two layered, feed forward architecture that learns relationships among unknown input data patterns. The prototype system consists of 25 processing units (neurons). Each processing unit operates at 10 MHz. Communication among processing units is accomplished using a broadcast bus. Performance of the system is estimated to be 110,000 iterations per second.< >

关键词： Very large scale integration Neural networks Unsupervised learning Image coding Computer architecture microelectronics Laboratories design engineering systems engineering and theory Focusing

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design and implementation of a fast and compact residue-based semi-custom VLSI arithmetic chip

Design and implementation of a fast and compact residue-base...

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Midwest Symposium on Circuits and systems (MWSCAS)

作者： A.A. Hiasat H.S. Abdel-Aty-Zohdy Department of Electrical and Systems Engineering Microelectronics Systems Design Laboratory Oakland University Rochester MI USA

design and implementation of a residue-based adder/subtractor/multiplier arithmetic TinyChip for the moduli set (2/sup n/-1,2/sup n/,2/sup n/+1) is addressed in this paper. The unit realization adopts CMOS semi-custom VLSI design, using Octtools-5.0 with the standard cell MSU2-3 library. The implemented chip has the advantage of reduced delay time and hardware requirements. Thus, it can support real-time one and two dimensional signal processing applications. The design does not have dynamic range limitations due to the absence of memory, therefore, this implementation can be expanded for better reliability. Performance of the system is estimated to be 18 million residue arithmetic operations per second on 2 /spl mu/m process.

关键词： Very large scale integration Arithmetic Signal processing algorithms Dynamic range Libraries Hardware Signal processing Logic Algorithm design and analysis microelectronics

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