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检索条件"机构=Microelectronics Systems Design Laboratory Department of Electrical and Computer Engineering"

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Notched ultra-wideband filter based on stepped-impedance T-shaped resonator in low temperature cofired ceramic

Notched ultra-wideband filter based on stepped-impedance T-s...

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IEEE International Wireless Symposium (IWS)

作者： Chun-Xia Zhou Yong-Xin Guo Lin-Sheng Wu Wen Wu Qian Xiao Ministerial Key Laboratory of JGMT Nanjing University of Science and Technology Nanjing China Department of Electrical and Computer Engineering National University of Singapore Singapore Key Lab of Ministry of Education for Research of Design and EMC of High-Speed Electronic Systems Shanghai Jiao Tong University Shanghai China

A compact ultra-wideband (UWB) bandpass filter with an inherent notched band and steep slopes has been presented and implemented with the low temperature cofired ceramic technology. The filter is realized by a stepped-impedance T-shaped resonator (SITR) coupled to a pair of quarter-wavelength input/output feed-lines. The proposed SITR can facilitate not only a notched band, but also sharp roll-off characteristics. Measured results agree well with the HFSS simulated results. The whole size of the UWB filter is only 6.0×6.0×1.92 mm 3 .

关键词： Band-pass filters Resonator filters Filtering theory Resonant frequency Ultra wideband technology Wireless communication Metals

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Rate adaptation and base station reconfiguration for battery efficient video download

Rate adaptation and base station reconfiguration for battery...

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IEEE Conference on Wireless Communications and Networking

作者： Ranjini Guruprasad Sujit Dey Mobile Systems Design Laboratory Department of Electrical and Computer Engineering University of California San Diego USA

ISBN: (纸本)9781467359382

With increasing usage of mobile devices to watch mobile video, the battery consumption of mobile devices will be dominated by video delivery and playback. In this paper, we develop battery efficient video delivery techniques that vary video transmission rate dynamically depending on battery and buffer levels of the mobile device, the channel conditions experienced, and video quality requirements while maximizing battery life and ensuring user experience. The proposed dynamic video rate adaptation techniques enable the base station to adapt the Multi Input Multi Output (MIMO) transceiver configurations to reduce battery current required by MIMO components on the mobile device. The proposed techniques also make the base station stop video transmission opportunistically, thereby eliminating the battery load imposed by the mobile MIMO components. Experiments conducted under various network conditions for various video download profiles show that more than 50% improvement in battery lifetime is possible in comparison to conventional video download techniques not aware of battery.

关键词： Batteries Streaming media Bit error rate MIMO Decoding Mobile handsets Signal to noise ratio

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Adaptive Bit Rate capable video caching and scheduling

Adaptive Bit Rate capable video caching and scheduling

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IEEE Conference on Wireless Communications and Networking

作者： Hasti Ahlehagh Sujit Dey Mobile Systems Design Laboratory Department of Electrical and Computer Engineering University of California San Diego USA

ISBN: (纸本)9781467359382

Adaptive Bit Rate Streaming (ABR) has become a popular video delivery technique, credited to improving the quality of delivered video on wireless networks. At the same time, recent research has shown video caching in the Radio Access Network (RAN) can be a promising way to increase capacity of the network while reducing video latency and improving video quality of experience. In this work, we investigate the opportunities and challenges of combining the advantages of ABR streaming and RAN caching to maximize the video capacity of wireless networks. Since with ABR, each video is divided into multiple segments, chunks, and each chunk can be requested at different bit rates, the caching requirements are very different and challenging; a cache hit will require not only the presence of a specific video chunk, but also the availability of the desired bit rate. One way to solve this problem is to cache all variants of a video, but this approach may significantly increase storage and backhaul requirements or reduce the number of unique videos that can be cached. In this paper, we introduce a framework consisting of rate adaptation algorithm, video caching and processing within the wireless cloud, with the aim to improve video capacity of the wireless network and satisfy or exceed QoE of each video request. To achieve this goal, we propose a new ABR algorithm, along with an ABR aware Least Recently Used (LRU) caching policy with Processing (ABRLRU-P) to support caching of video chunks with different bit rates. Using our MATLAB statistical simulation framework, we demonstrate a capacity improvement of up to 83% when ABR is used with RAN caching and processing using the ABR-LRU-P policy compared with using no RAN caching and video processing. Further, using ABR along with ABRLRU-P caching policy can improve the capacity by 68% compared with using ABR and a straightforward static LRU caching policy which fetches all video bit rate versions of a video chunk upon a cache miss.

关键词： Streaming media Bit rate Delays Wireless networks Radio access networks Bandwidth

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An efficient hybrid scheduling scheme for impatience user in eMBMS over LTE

An efficient hybrid scheduling scheme for impatience user in...

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International Conference on computer Communication and Informatics (ICCCI)

作者： Rochak Sachan Navrati Saxena Abhishek Roy Department of Electrical and Computer Engineering Sungkyunkwan University Suwon South Korea System Design Laboratory Telecom Systems Division Samsung Electronics Suwon South Korea

ISBN: (纸本)9781467329064

The 3 rd Generation Partnership Project - Long Term Evolution (3GPP-LTE) is the best choice for multimedia data transmission in demanding situation. The 3GPP LTE provides high data transmission rate between the User Equipment (UE) and Evolved Node B (eNB) with lower latency and better throughput. However, with the advancement and increasing traffic of data load, it is necessary to have data scheduling with user requests. In real life situations, mobile users become impatient when they don't receive their desired data. Moreover, the LTE Enhanced Multimedia Broadcast Multicast Services (eMBMS) does not provide any type of scheduling to measure and manage the impatient user request in multimedia broadcasting scenario. So, we consider this situation in our proposed scheme and simulated a new type of hybrid scheduling scheme to overcome this problem. It also takes care of the server anomalies arising from multiple requests sent by the same user for the same data.

关键词： Optimal scheduling Multimedia communication Quality of service Data communication computers Servers Informatics

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Improved supervision of NN's AOA determination with limited 1-D phased-array training data

Improved supervision of NN's AOA determination with limited ...

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2011 IEEE National Aerospace and Electronics Conference, NAECON 2011

作者： Van Sickle, Kevin Abdel-Aty-Zohdy, Hoda S. Microelectronics and Bio-Inspired Systems Design Lab. Department of Electrical and Computer Engineering Oakland University Rochester MI United States

ISBN: (纸本)9781457710407

A sixteen-channel linear phased array radar is calibrated by means of Artificial Neural Network (ANN). Limited data are used to train the various layers of the network, for Angle of Arrival (AOA) determinacy. This is designed to increase speed of operation and to prevent over fitting. The designed simulator generates time-series data sets representing continuous span of AOA. The generated datasets are used in multilayer feedforward NNs to find the phase, which is then used as inputs to Spiking Neural Network (SNN) o determine AOA. SNNs are used for hardware implementation feasibility. The designed simulator improved the accuracy of AOA determination, and opens the door for a wide variety of radar classification applications © 2011 IEEE.

关键词： Neural networks

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A parallel Ray Tracing architecture suitable for application-specific hardware and GPGPU implementations

A parallel Ray Tracing architecture suitable for application...

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2011 14th Euromicro Conference on Digital System design: Architectures, Methods and Tools, DSD 2011

作者： Nery, Alexandre S. Nedjah, Nadia Franca, Felipe M.G. Jozwiak, Lech LAM - Computer Architecture and Microelectronics Laboratory Systems Engineering and Computer Science Program COPPE Universidade Federal Rio de Janeiro Brazil Department of Electronics Engineering and Telecommunications Faculty of Engineering Universidade do Estado Rio de Janeiro Brazil Department of Electrical Engineering - Electronic Systems Eindhoven University of Technology Netherlands

ISBN: (纸本)9780769544946

The Ray Tracing rendering algorithm can produce high-fidelity images of 3-D scenes, including shadow effects, as well as reflections and transparencies. This is currently done at a processing speed of at most 30 frames per second. Therefore, actual implementations of the algorithm are not yet suitable for interactive real-time rendering, which is required in games and virtual reality based applications. Fortunately, the algorithm allows for massive parallelization of its computations. In this paper, we present a parallel architecture for ray tracing based on a uniform spatial subdivision of the scene and exploiting an embedded computation of ray-triangle intersections. This approach allows for a significant acceleration of intersection computations, as well as, a reduction of the total number of the required intersections checks. Furthermore, it allows for these checks to be performed in parallel and in advance for each ray. In this paper we discuss and analyze an ASIP-based implementation using FPGAs and a GPGPU-based parallel implementation of the proposed architecture. The performance of both implementations are reported and compared." © 2011 IEEE.

关键词： Ray tracing

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Improved supervision of NN's AOA Determination with limited 1-D Phased-Array Training Data

Improved supervision of NN's AOA Determination with limited ...

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IEEE National Aerospace and Electronics Conference

作者： Kevin Van Sickle Hoda S. Abdel-Aty-Zohdy Microelectronics & Bio-Inspired Systems Design Lab Department of Electrical and Computer Engineering Oakland University

ISBN: (纸本)9781457710407

A sixteen-channel linear phased array radar is calibrated by means of Artificial Neural Network (ANN). Limited data are used to train the various layers of the network, for Angle of Arrival (AOA) determinacy. This is designed to increase speed of operation and to prevent over fitting. The designed simulator generates time-series data sets representing continuous span of AOA. The generated data-sets are used in multilayer feed-forward NNs to find the phase, which is then used as inputs to Spiking Neural Network (SNN) o determine AOA. SNNs are used for hardware implementation feasibility. The designed simulator improved the accuracy of AOA determination, and opens the door for a wide variety of radar classification applications.

关键词： Simulation SNN AOA Phased Array Training-Based Limited Data Set Classification ANGLE OF ATTACK SNN gene phased array simulating hierarchical network Continuous spans

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Hardware reuse in modern application-specific processors and accelerators

Hardware reuse in modern application-specific processors and...

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2011 14th Euromicro Conference on Digital System design: Architectures, Methods and Tools, DSD 2011

作者： Nery, Alexandre S. Jozwiak, Lech Lindwer, Menno Cocco, Mauro Nedjah, Nadia França, Felipe M.G. LAM - Computer Architecture and Microelectronics Laboratory Systems Engineering and Computer Science Program COPPE Universidade Federal do Rio de Janeiro Brazil Department of Electronics Engineering and Telecommunications Faculty of Engineering Universidade do Estado do Rio de Janeiro Brazil Department of Electrical Engineering - Electronic Systems Eindhoven University of Technology Netherlands Silicon Hive - Intel UMG Netherlands

ISBN: (纸本)9780769544946

Effective exploitation of the application-specific parallel patterns and computation operations through their direct implementation in hardware is the base for construction of high-quality application-specific (re-) configurable application specific instruction set processors (ASIPs) and hardware accelerators for modern highly-demanding applications. Although it receives a lot of attention from the researchers and practitioners, a very important problem of hardware reuse in ASIP and accelerator synthesis is clearly underestimated and does not get enough attention in the published research. This paper is an effect of an industry and academic collaborative research. It analyses the problem of hardware sharing, shows its high practical relevance, as well as a big influence of hardware sharing on the major circuit and system parameters, and its importance for the multi-objective optimization and tradeoff exploitation. It also demonstrates that the state-of-the-art synthesis tools do not sufficiently address this problem and gives several guidelines related to enhancement of the hardware reuse. © 2011 IEEE.

关键词： Multiobjective optimization

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Chip-to-wafer (C2W) 3D integration with well-controlled template alignment and wafer-level bonding

Chip-to-wafer (C2W) 3D integration with well-controlled temp...

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Electronic Components and Technology Conference (ECTC)

作者： Qianwen Chen Dingyou Zhang Zheyao Wang Litian Liu James Jian-Qiang Lu Department of Electrical Computer and Systems Engineering Rensselaer Polytechnic Institute Troy NY USA Tsinghua National Laboratory for Information Science and Technology (TNList) Institute of Microelectronics Tsinghua University Beijing China

This paper presents on a novel chip-to-wafer (C2W) three-dimensional (3D) integration technology with well-controlled template alignment and wafer-level bonding, enabling precise alignment, few thermal cycles and high throughput of 3D system fabrication. The key processes are investigated and discussed in detail, including chip edge definition, template fabrication, C2W alignment and wafer-level bonding. The C2W 3D integration technology is successfully demonstrated using Cu daisy chains, a patterned thick benzocyclobutene (BCB) layer on the wafer as the alignment template, and wafer-level C2W Cu-Cu bonding. An alignment accuracy less than 2 μm is achieved. The FIB-SEM images reveal that Cu grains cross the original Cu-Cu bonding interface to form strong bonding. The measured I-V characteristics of daisy chains show a linear ohmic behavior, and the specific contact resistance of Cu-Cu bonding structures is on the order of 10 -8 ohm-cm 2 , suggesting good electric contacts.

关键词： Bonding Copper Three dimensional displays Etching Accuracy Resistance

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IPF: In-Place X-Filling to Mitigate Soft Errors in SRAM-Based FPGAs

IPF: In-Place X-Filling to Mitigate Soft Errors in SRAM-Base...

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International Conference on Field Programmable Logic and Applications

作者： Zhe Feng Naifeng Jing GengSheng Chen Yu Hu Lei He Electrical Engineering Department University of California Los Angeles USA School of Microelectronics Shanghai Jiao Tong University China State Key Laboratory of Application Specific Circuits and Systems Fudan University Shanghai China Electrical and Computer Engineering Department University of Alberta Canada

SRAM-based Field Programmable Gate Arrays (FPGAs) are vulnerable to Single Event Upsets (SEUs). We show that a large portion (40%-60% for the circuits in our experiments) of the total used LUT configuration bits are don't care bits, and propose to decide the logic values of don't care bits such that soft errors are reduced. Our approaches are efficient and do not change LUT level placement and routing. Therefore, they are suitable for design closure. For the ten largest combinational MCNC benchmark circuits mapped for 6-LUTs, our approaches obtain 20% chip level Mean Time To Failure (MTTF) improvements, compared to the baseline mapped by Berkeley ABC mapper. They obtain 3× more chip level MTTF improvements and are 128× faster when compared to the existing best in-place IPD algorithm.

关键词： Table lookup Field programmable gate arrays Integrated circuit interconnections Integrated circuit reliability Observability Helium

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