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design methodology for wireless nodes with printed antennas

Design methodology for wireless nodes with printed antennas

引用

42nd design Automation Conference, DAC 2005

作者： Chenard, Jean-Samuel Žilić, Željko Chu, Chun Yiu Popović, Milica Department of Electrical and Computer Engineering McGill University Montréal Qué. Canada Microelectronics and Computer Systems Laboratory Canada Computational Electromagnetics Software Laboratory Canada

The need for mass-produced inexpensive wireless devices operating under strict energy constraints poses new challenges in the system design methodology. This paper presents a methodology for designing wireless nodes in which a low cost, reliable antenna is realized by printed circuit traces. We show how to combine the analysis from 2.5D and 3D EM simulators with the PCB design tools to create predictable nodes with printed antennas that meet stringent power and data transmission range goals. The presented approach is applied to the design of a IEEE802.15.4 wireless node deployed in several indoor environments. Copyright 2005 ACM.

关键词： Wireless telecommunication systems

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Modeling layout effects for sensitivity-based analog circuit optimization

Modeling layout effects for sensitivity-based analog circuit...

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IEEE International Symposium on Quality Electronic design

作者： H.H.Y. Chan Z. Zilic Department of Computer and Electrical Engineering Microelectronics and Computer Systems Laboratory Montreal QUE Canada

Successful deep-submicron designs require significant computation resources for thorough signal and design integrity analysis. Rising quality expectations and shortening time-to-market requirements present additional challenges for design closure. Conventional analog circuit optimizers are efficient in circuit analysis and optimization. Due to recent promising results, designers are beginning to adopt automated physical synthesis in their condensed development cycles in order to improve their prototyping efficiency. For high-performance circuit optimization, idealized performance as well as parasitic data should also be considered. This paper presents an effective framework to incorporate parasitic effects into a sensitivity-based circuit optimization tool. To relieve the physical synthesis bottleneck, estimations of parasitic values based on past extraction results are made during incremental design changes. Sensitivities of the performance impact can then be computed efficiently. As a result physical performance can be optimized using available optimizer and synthesis tools without the need of a priori expert rules, knowledge or cell libraries.

关键词： Analog circuits Circuit synthesis Signal design Circuit optimization Signal analysis Time to market Circuit analysis Signal synthesis Prototypes Data mining

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Energy diffusion model of bR for voxel identification

Energy diffusion model of bR for voxel identification

引用

Midwest Symposium on Circuits and systems (MWSCAS)

作者： D. Garcia Neto H.S. Abdel-Aty-Zohdy Microelectronics System Design Laboratory-Department of Electrical and Systems Engineering Oakland University Rochester USA

In this paper, a potential biological structure for computer volumetric memory is investigated. Bacteriorhodopsin is a protein found in the purple membrane of the bacteria Halobacterium salinarum. This protein has light absorption properties that generate different stable states allowing the use of multilevel logic as well as binary logic. CHARMmtrade has been used to simulate the energy response of Bacteriorhodopsin at room temperature 300K for the bR ground state and the other states. The K state takes place after blue light (lambda= 635nm) absorption on the bR state. The energy difference is found to be an increase of 1086.92 kcal/mol which is responsible for triggering the photocycle that also includes the states K, L, M, N, and O. An energy surplus is found between O and bR state that may be spread to surrounding molecules. However, conformational interference does not produce photons necessary for the isomerization reaction. Further quantum molecular (QM) analysis should provide an extended model for this macromolecular energy study

关键词： Biological system modeling Proteins Absorption Logic Biology computing Biomembranes Microorganisms Computational modeling Land surface temperature Stationary state

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High speed systems engineering: A new trent in electrical and computer engineering

High speed systems engineering: A new trent in electrical an...

引用

2005 ASEE Annual Conference and Exposition: The Changing Landscape of engineering and Technology Education in a Global World

作者： Mina, Mani Weber, Robert Somani, Arun K. VanderHorn, Nathan Bahuguna, Rashmi High Speed Systems Engineering Laboratory Department of Electrical and Computer Engineering Iowa State University United States Iowa State University United States Analog and Mixed-Signal VLSI Design Center United States

The main ideas and objectives of High Speed systems engineering (HSSE) are presented. HSSE is being used as integrating pedogogical and research platforms to train modern engineers and future researchers. The newly developed classes and the changes made in the curriculum is enhancing interaction between faculty, graduate and undergraduate students. A study shows that HSSE has been successful in encouraging students from all undergraduate levels to participate in learning and experimenting, also are encouraged to be involved in research and graduate studies.

关键词： systems engineering

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2.40-2.48 GHz bandpass filter in 0.18 /spl mu/m CMOS

2.40-2.48 GHz bandpass filter in 0.18 /spl mu/m CMOS

引用

IEEE International Workshop on Radio-Frequency Integration Technology (RFIT)

作者： R.C. Yadav K.S. Lee V. Bharadwaj Integrated Circuits and Systems Laboratory Institute of Microelectronics Singapore Department of Electrical and Computer Engineering National University of Singapore Singapore

A band-pass filter operating in 2.40 GHz to 2.48 GHz range is designed in 0.18 /spl mu/m CMOS technology. It has tunable center frequency, Q-factor and gain. The fully integrated system-on-chip (SOC) 10th order band-pass filter is built by cascading five stages of 2nd order. The simulation of the filter on ADS software provides an insertion gain of 8 dB in the pass-band frequency from 2.40 GHz to 2.48 GHz. The attenuation in the stop-band is observed to be higher than 50 dB at 400 MHz away from pass-band edge with 15 mA current sinking from a 1.8 V supply. We present several simulation results to highlight these characteristics.

关键词： Band pass filters Frequency Circuits MOSFETs Inductors Q factor CMOS technology Impedance Reflection Resistors

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Equalizing data-path for processing speed determination in block level pipelining

Equalizing data-path for processing speed determination in b...

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IEEE International Symposium on Circuits and systems (ISCAS)

作者： Xiaoyao Liang A. Athalye Sangjin Hong Mobile Systems Design Laboratory Department of Electrical and Computer Engineering Stony Brook University-SUNY Stony Brook NY USA

Signal processing algorithms represented by data flow graphs can be efficiently mapped to hardware using a block level pipelining architecture. In this scheme, nodes of data flow are mapped to processing blocks and buffers are inserted in between as pipelining elements. We present, in this paper, a methodology for equalizing execution times of various nodes in the data path. The method is used to minimize the power dissipation and buffer usage by judiciously selecting the execution speed of hardware units. The block level pipelining allows for simple local controllers for each buffer which are generated by the global controller based on data flow specifications. The evaluation of the methodology on a practical example is presented.

关键词： Pipeline processing Communication system control Signal processing algorithms Control systems Hardware Centralized control Frequency synchronization Distributed control Mobile computing Laboratories

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Dynamic coarse grain dataflow reconfiguration technique for real-time systems design

Dynamic coarse grain dataflow reconfiguration technique for ...

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IEEE International Symposium on Circuits and systems (ISCAS)

作者： Xiaoyao Liang A. Athalye Sangjin Hong Mobile Systems Design Laboratory Department of Electrical and Computer Engineering Stony Brook University-SUNY Stony Brook NY USA

The paper explores a reconfigurable platform design methodology for high throughput execution of data centric applications. The reconfiguration platform consists of heterogenous processing elements and buffers interacting through reconfigurable interconnects. The proposed platform is based on block level pipelining with the buffers and their respective controllers forming the pipelining elements. We discuss the dynamic and partial reconfiguration techniques of this platform. Specifically, reconfiguration overhead at runtime is illustrated.

关键词： Real time systems Switches Integrated circuit interconnections computer architecture Pipeline processing Reconfigurable architectures design methodology Throughput Digital signal processing Parallel processing

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Minimization of secondary effects in SOI: a 32-bit ANT logic adder implementation

Minimization of secondary effects in SOI: a 32-bit ANT logic...

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Midwest Symposium on Circuits and systems (MWSCAS)

作者： A. Wasson Dipti Sanghvi A. Nunez VLSI Systems Design and CAD (VSDCAD) Laboratory Department of Electrical Engineering and Computer Science (EECS) Syracuse University Syracuse NY USA

This paper presents a review of circuit design techniques related to silicon on insulator technology (SOI) CMOS circuits. The most important design considerations are parasitic bipolar effect, floating body effect and hysteric variation in the threshold voltage. These effects lead to the reduction of the noise margin and under serious circumstances may lead to a wrong output. Dynamic circuits are most vulnerable to these effects due to the presence of a soft node at the top of the pull down stack. We have studied the various existing techniques and have proposed a design modification which alleviates the floating body effect without compromising other parameters like speed and without penalizing the charge sharing present. The approach is based on adding an extra transistor which will minimize the floating body effect without worsening charge sharing. The effectiveness of our design technique is demonstrated through its implementation in a 32-bit ANT logic carry look ahead adder using BSIMSOI models. Results show that the performance of the modified circuit is reliable and minimizes the floating body effect without adversely affecting charge sharing

关键词： Minimization Silicon on insulator technology Adders CMOS logic circuits Circuit synthesis CMOS technology Threshold voltage Noise reduction Circuit noise Logic design

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Pre-layout parasitic estimation in interconnects

Pre-layout parasitic estimation in interconnects

引用

Midwest Symposium on Circuits and systems (MWSCAS)

作者： S. Shah A. Nunez Department of Electrical Engineering and Computer Science (EECS) VLSI Systems Design and CAD (VSDCAD) Laboratory Syracuse University Syracuse NY USA

Interconnect lengths have become a dominant factor in the design of integrated circuits. The parasitics associated with the interconnects account for a significant part of signal delay. The estimation of interconnect lengths prior to placement helps in determining the delay early in the design phase. In this paper, a methodology to estimate the interconnect lengths prior to layout, is presented. The approach is heuristics based. Various layouts have been studied to observe typical placement and routing patterns. The methodology uses the gate level netlist and properties of the cells obtained from the standard cell libraries for the estimation. The results have been compared with the detailed routing wire lengths obtained after synthesis of the gate level netlist. Cadence Buildgates was used for syntheises and Cadence Encounter used for placement and routing of the circuits. The methodology presented is independent of the technology being used. However the wire lengths will vary with the use of different placement and routing tools

关键词： Integrated circuit interconnections Wire Delay estimation Routing Circuit synthesis Capacitance Libraries Optimization methods Pins Very large scale integration

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An analysis of expressiveness and design issues for the generalized temporal role-based access control model

An analysis of expressiveness and design issues for the gene...

引用

作者： Joshi, James B. D. Bertina, Elisa Ghafoor, Arif Department of Information Sciences and Telecommunications University of Pittsburgh Pittsburgh PA 15260 United States Department of Computer Science Purdue University West Lafayette IN 47907 United States School of Electrical and Computer Engineering Purdue University West Lafayette IN 47907 United States Department of Information Sciences and Telecommunications School of Information Sciences University of Pittsburgh United States University of Pittsburgh United States Computer Science Department Purdue University United States CERIAS United States San Jose CA United States Microelectronics and Computer Technology Corporation Rutgers University Telcordia Technologies United States School of Electrical and Computer Engineering Purdue University West Lafayette IN United States Distributed Multimedia Systems Laboratory Information Infrastructure Security Research Laboratory United States

The Generalized Temporal Role-Based Access Control (GTRBAC) model provides a comprehensive set of temporal constraint expressions which can facilitate the specification of fine-grained time-based access control policies. However, the issue of the expressiveness and usability of this model has not been previously investigated. In this paper, we present an analysis of the expressiveness of the constructs provided by this model and illustrate that its constraints-set is not minimal. We show that there is a subset of GTRBAC constraints that is sufficient to express all the access constraints that can be expressed using the full set. We also illustrate that a nonminimal GTRBAC constraint set can provide better flexibility and lower complexity of constraint representation. Based on our analysis, a set of design guidelines for the development of GTRBAC-based security administration is presented. © 2005 IEEE.

关键词： Security of data

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