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A 1-V, 10-bit rail-to-rail successive approximation analog-to-digital converter in standard 0.18 /spl mu/m CMOS technology

A 1-V, 10-bit rail-to-rail successive approximation analog-t...

引用

IEEE International Symposium on Circuits and systems (ISCAS)

作者： C.J.B. Fayomi G.W. Roberts M. Sawan Department of Electrical and Computer Engineering Ecole Polytechnique de Montreal Montreal Canada Microelectronics and Computer Systems Laboratory McGill University Montreal Canada

ISBN: (纸本)0780366859

Two architectures for a 1-V, 10-bit 200-kS/s successive approximation analog-to-digital converter (ADC) implemented in a standard CMOS 0.18 /spl mu/m digital process are presented. A track-and-hold circuit based on a novel implementation of the bootstrapped low-voltage analog CMOS switch with a novel rail-to-rail track-and-latch comparator circuit is described. A pMOS-only ladder containing a rail-to-rail current-to-voltage converter, performs the DAC function in the second ADC topology whereas a conventional R-2R ladder is used in the first one. Successive approximation and control logic is implemented using of robust single clock phase D flip flop.

关键词： Analog-digital conversion CMOS technology Circuits Power supplies CMOS process Threshold voltage Dynamic range Wide area networks microelectronics Laboratories

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A 1-V, 10-bit rail-to-rail successive approximation analog-to-digital converter in standard 0.18 μm CMOS technology

A 1-V, 10-bit rail-to-rail successive approximation analog-t...

引用

2001 IEEE International Symposium on Circuits and systems, ISCAS 2001

作者： Fayomi, Christian Jesus B. Roberts, Gordon W. Sawan, Molianiad Ecole Polytechnique de Montreal Department of Electrical and Computer Engineering Station Centre Ville P.0 Box 6079 Montreal H3C 3A7 Canada Microelectronics and Computer Systems Laboratory McGill University Montreal H3A 2A7 Canada

ISBN: (纸本)0780366859

Two architectures for a 1-V, 10-bit 200-kS/s successive approximation analog-to-digital converter (ADC) implemented in a standard CMOS 0.18 μm digital process are presented. A track-and-hold circuit based on a novel implementation of the bootstrapped low-voltage analog CMOS switch with a novel rail-to-rail track-and-latch comparator circuit is described. A pMOS-only ladder containing a rail-to-rail current-to-voltage converter, performs the DAC function in the second ADC topology whereas a conventional R-2R ladder is used in the first one. Successive approximation and control logic is implemented using of robust single clock phase D flip flop. © 2001 IEEE.

关键词： Ladders

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Integrated hardware-software co-synthesis for design of embedded systems under power and latency constraints 01

Integrated hardware-software co-synthesis for design of embe...

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Proceedings of the conference on design, automation and test in Europe

作者： A. Doboli VLSI Systems Design Laboratory Department of Electrical and Computer Engineering State University of New York (SUNY) at Stony Brook Stony Brook NY

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Integrated hardware-software co-synthesis and high-level synthesis for design of embedded systems under power and latency constraints

Integrated hardware-software co-synthesis and high-level syn...

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design, Automation and Test in Europe Conference and Exhibition

作者： A. Doboli VLSI Systems Design Laboratory Department of Electrical and Computer Engineering State University of New York Stony Brook Stony Brook NY USA

ISBN: (纸本)0769509932

This paper presents an integrated approach to hardware software co-synthesis and HLS for design of low-power embedded systems. The main motivation for this work is that fine trade-offs between latency and power can be explored at the system level only with a detailed knowledge of used hardware resources. Integrated method was realized as a simulated annealing based solution-space exploration. Exploration is guided by Performance Models, that exactly capture the relationship between performances i.e. power consumption and latency and design decisions i.e. binding and scheduling. The proposed approach permits nor only a more accurate latency and power estimation but also the exposure of RTL-level design decisions at the system level. As a result, more effective power-latency trade-offs are possible during co-synthesis as compared to traditional task-level methods.

关键词： High level synthesis Embedded system Delay Hardware Power system modeling Energy consumption Very large scale integration Laboratories Embedded software Annealing

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An asynchronous FIFO with fights: case study in speed optimization

An asynchronous FIFO with fights: case study in speed optimi...

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IEEE International Conference on Electronics, Circuits and systems (ICECS)

作者： S. Laberge R. Negulescu Microelectronics and Computer Systems Laboratory Department of Electrical and Computer Engineering McGill University Montreal QUE Canada

ISBN: (纸本)0780365429

This paper describes an experiment in optimizing digital integrated circuits to maximize operating speeds. The circuit in question is an asynchronous FIFO originally designed for ultra-high-speed. To obtain an even higher throughput, we consider optimizations and local changes of the circuits by using fights, relative delay constraints, and asymmetric and skewed gates. We propose a transistor sizing procedure applicable in these conditions. Part of our procedure is based on the principles of logical effort; in addition, we investigate how to size the circuit with fights. The resulting circuit implemented in TSMC's 0.35 /spl mu/m technology can yield throughputs over 1500 millions items per second.

关键词： computer aided software engineering Delay Throughput Logic circuits Capacitance Equations microelectronics Laboratories Digital integrated circuits Constraint optimization

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A robust deep submicron programmable DC voltage generator

A robust deep submicron programmable DC voltage generator

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IEEE International Symposium on Circuits and systems (ISCAS)

作者： M.M. Hafed S. Laberge G.W. Roberts Microelectronics and Computer Systems Laboratory Department of Electrical and Computer Engineering McGill University Montreal QUE Canada

An efficient technique for generating accurate on-chip DC reference voltages is presented. The technique is based on filtering a digital pulse-modulated sequence in order to extract its average (DC) value. Simplicity is achieved by using a passive on-chip filter and by using an all-digital implementation of the modulator. Moreover, in addition to using pulse-width modulation to encode the value of the output DC level, we propose the use of pulse-density modulation as a more viable technique. The latter has the advantage of using a significantly smaller filter, which translates into a smaller implementation area and a faster settling time. The technique was successfully demonstrated using a prototype IC in a 0.35 /spl mu/m CMOS process.

关键词： Robustness Voltage DC generators Pulse modulation Digital filters Filtering Passive filters Space vector pulse width modulation Prototypes CMOS integrated circuits

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A stand-alone integrated excitation/extraction system for analog BIST applications

A stand-alone integrated excitation/extraction system for an...

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Custom Integrated Circuits Conference (CICC)

作者： M.M. Hafed G.W. Roberts Microelectronics and Computer Systems Laboratory Department of Electrical and Computer Engineering McGill University Montreal QUE Canada

An integrated test core for mixed-signal circuits is described. The core consists of a completely digital implementation, except for a simple reconstruction filter and a comparator. It is capable of both generating arbitrary band-limited waveforms (for excitation purposes) and coherently digitizing arbitrary periodic analog waveforms (for DSP-based test and measurement). A prototype IC was fabricated in a 0.35 /spl mu/m CMOS process and was demonstrated to perform various curve tracing, oscilloscope, and spectrum analysis tasks.

关键词： Built-in self-test Circuit testing Signal generators Application software Hardware Band pass filters microelectronics Laboratories System testing Digital filters

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A maintainability model for industrial software systems using design level metrics

A maintainability model for industrial software systems usin...

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Working Conference on Reverse engineering

作者： S. Muthanna K. Kontogiannis K. Ponnambalam B. Stacey Department of Electrical & Computer Engineering University of Waterloo Waterloo ONT Canada Nortel SEAL Laboratory University of Waterloo Ottawa Canada Department of Systems Design Engineering University of Waterloo Waterloo ONT Canada

ISBN: (纸本)0769508812

Software maintenance is a time consuming and expensive phase of a software product's life-cycle. The paper investigates the use of software design metrics to statistically estimate the maintainability of large software systems, and to identify error prone modules. A methodology for assessing, evaluating and, selecting software metrics for predicting software maintainability is presented. In addition, a linear prediction model based on a minimal set of design level software metrics is proposed. The model is evaluated by applying it to industrial software systems.

关键词： computer industry Software systems Software design Software maintenance Software metrics Software quality Maintenance engineering design engineering Seals Predictive models

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Low power/low voltage high speed CMOS differential track and latch comparator with rail-to-rail input

Low power/low voltage high speed CMOS differential track and...

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IEEE International Symposium on Circuits and systems (ISCAS)

作者： C.J.B. Fayomi G.W. Roberts M. Sawan Dept. of Electr. & Comput. Eng. Ecole Polytech. Montreal Que. Canada Microelectronics and Computer Systems Laboratory McGill University Montreal Canada Department of Electrical and Computer Engineering Ecole Polytechnique de Montreal Montreal Canada

A new CMOS differential latched comparator suitable for low voltage, low-power application is presented. The circuit consists of constant-gm rail-to-rail common-mode operational transconductance amplifier followed by a regenerative latch in a track and latch configuration to achieve a relatively constant delay. The use of a track and latch minimizes the total number of gain stages required for a given resolution. Potential offset from the constant-g/sub m/ differential input stage, estimated as the main source of offset, can be minimized by proper choice of transistors sizes. Simulation results show that the circuit requires less than 86 /spl mu/A with a supply voltage of 1.65 V in a standard CMOS 0.18 /spl mu/m digital process. The average delay is less than 1 ns and is approximately independent of the common-mode input voltage.

关键词： Low voltage Latches Delay Rail to rail operation Transconductance Operational amplifiers Rail to rail amplifiers Circuit simulation CMOS digital integrated circuits CMOS process

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Analog computational circuits for neural network implementations

Analog computational circuits for neural network implementat...

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IEEE International Conference on Electronics, Circuits and systems (ICECS)

作者： M. Al-Nsour H.S. Abdel-Aty-Zohdy Microelectronics System Design Laboratory Department of Electrical and Systems Engineering Oakland University Rochester MI USA

High performance NMOS analog circuits which perform voltage addition, average weighing, and signal scaling are presented. Utilization of these circuits in artificial neural network applications is briefly discussed. The circuits are characterized by a simple structure which offers compactness, low voltage supply, and wide input range. In addition, inputs and outputs are voltages which eliminate the need for current voltage conversion. Hence, reduced power consumption and higher performance is achieved. A two-input analog adder has been accomplished through MOSIS 2.0 /spl mu/m n-well CMOS technology at Orbit Semiconductors, and occupies an area of 135/spl times/145 /spl mu/m/sup 2/. Inputs are within /spl plusmn/3 V for 3.3 V supply. Power consumption is less than 0.5 mW and THD is less than -36 dB. Measurements and performance evaluation are presented.

关键词： Analog computers computer networks Neural networks Artificial neural networks Energy consumption CMOS technology MOS devices Analog circuits Low voltage Adders

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