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International Conference on Information, Communications and Signal Processing

作者： A.Z.R. Langi K. Soemintapura T.L. Mengko W. Kinsner Laboratory of Microelectronics Desigu InterUniversity Microelectronics Centre Belgium Laboratory for Signals and Systems Department of Electrical Engineering Institute of Technology Bandung West Java Indonesia Department of Electrical and Computer Engineering University of Manitoba Winnipeg MAN Canada

This paper proposes image quality measures based on multifractality preservation. Image quality measures play critical roles in designing and evaluating image processing schemes and performance, especially in which the resulting images deviate from the original ones. Examples of such schemes include image denoising and lossy compression. Traditional quality or distortion measures have been based on mean square error (MSE) measure or its derivatives, e.g., signal to noise ratio (SNR) or peak SNR (PSNR). Although such measures often lead to optimal schemes (with respect to MSE or PSNR), they are known to remove image parts that has noise-like appearances. Furthermore, they treat image singularities such as sharp edges or high textures (that are more important visually and diagnostically) and other image parts (that are less important) uniformly. In contrast, multifractal measures proposed in this paper characterize image singularities. This means the measures pay attention more on important image features, such as sharp edges and high textures. Furthermore, it can distinguish noise from noise-like signals through their differences in their types of singularities. As a result, the measure can be used to assess image quality of sensitive images resulting from processing schemes. The paper shows various ways of defining the measure that reveals multifractality of different aspects of images. It reports the use of the multifractal measure to compare a joint photographic expert group (JPEG) scheme and a variant of differential pulse code modulation (DPCM) coding showing that the DPCM scheme is superior in multifractal preservation for comparable compression ratios. As a result, the DPCM coding has been selected for a database of aerial ortho images.

关键词： Fractals Image quality Distortion measurement Image coding Noise measurement Signal to noise ratio PSNR Pulse measurements Pulse modulation Image processing

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Modeling reverse short channel and narrow width effects in small size MOSFET's for circuit simulation

Modeling reverse short channel and narrow width effects in s...

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International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)

作者： Yuhua Cheng T. Sugii Kai Chen Zhihong Liu Min-Chie Jeng Chenming Hu Department of Electrical Engineering and Computer Sciences University of California Berkeley CA USA ULSI Technology Laboratory Fujitsu Laboratories Limited Atsugi Japan BTA Technologies Inc. Santa Clara CA USA Cadence Design Systems Santa Clara CA USA

Modeling of small size MOSFETs and experimental verification of the model using devices with varying pocket implant processes are presented. The results show that the model can describe reverse short channel and narrow width effects and match the measured characteristics of threshold voltage and saturation current over a wide range of channel lengths and widths down to 0.12 /spl mu/m regime.

关键词： MOSFET circuits Circuit simulation Threshold voltage Implants Semiconductor process modeling Doping Length measurement Data mining Solid modeling Immune system

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A frequency response, harmonic distortion, and intermodulation distortion test for BIST of a sigma-delta ADC

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IEEE TRANSACTIONS ON CIRCUITS AND systems II-ANALOG AND DIGITAL SIGNAL PROCESSING 1996年第8期43卷 608-613页

作者： Toner, MF Roberts, GW Microelectronics and Computer Systems Laboratory Department of Electrical Engineering McGill University Montreal Canada

Built-In-Self-Test (BIST) for VLSI systems is desirable for production-time testing and in-the-field diagnostics, This brief discusses a Mixed Analog-Digital BIST (MADBIST) for a frequency response test, a harmonic distortion test and an intermodulation distortion test of an analog-to-digital converter, The MADBIST strategy for the frequency response, harmonic distortion, and intermodulation distortion tests of the ADC is introduced, accuracy issues are discussed, and preliminary experimental results are presented.

关键词： Frequency response Harmonic distortion Intermodulation distortion Built-in self-test Cellular neural networks Neural networks Circuit testing Cellular networks Optical interconnections Optical receivers

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Transparent random access memory testing for pattern sensitive faults

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JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS 1996年第3期9卷 251-266页

作者： Karpovsky, MG Yarmolik, VN Research Laboratory of Design and Testing of Computer Hardware Department of Electrical Computer and Systems Engineering Boston University Boston USA

This paper presents a new methodology for RAM testing based on the PS(n, k) fault model (the k out of n pattern sensitive fault model). According to this model the contents of any memory cell which belongs to an n-bit memory block, or the ability to change the contents, is influenced by the contents of any k-1 cells from this block. The proposed methodology is a transparent BIST technique, which can be efficiently combined with on-line error detection. This approach preserves the initial contents of the memory after the rest and provides for a high fault coverage for traditional fault and error models, as well as for pattern sensitive faults. This paper includes the investigation of testing approaches based on transparent pseudoexhaustive testing and its approximations by deterministic and pseudorandom circular tests. The proposed methodology can be used for periodic and manufacturing testing and require lower hardware and time overheads than the standard approaches.

关键词： random access memory memory testing exhaustive memory testing transparent memory testing built-in self-test pseudo-exhaustive memory testing pattern sensitive faults signature analysis

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Operational systems, logistics engineering and technology insertion

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NAVAL ENGINEERS JOURNAL 1997年第3期109卷 205-220页

作者： Grubb, MJ Skolnick, A Michael J. Grubb:has perfomzed naval engineering at the Crane Division Naval Surface Warfare Center (NSWC) for more than twenty-five years. He currently the program manager for the Sustainable Hardware and Affordable Readiness Practice Program (SHARP). is a Navy-wide logistics research and development prgram aimed at the successful transiton of proved technologies inot the fleet. SHARP focuses on reducing acquisition performance capability reliability maintainability and readiness of these systems. Mr. Grubb has served as a department director for the past eleven years. His most recent assignment was as director of the Tactical Computer Resources and Test Equipment Department. This organization provided acquisition and in-service engineering support of the Navy's tectical embedded computers priphirals displays and mass memory storage devices. The organization also provided a complete range of product engineering and metrology engineerig services for SSP NevSeaSysCom and the Trident Program. Prior to this appointment Mr. Grubb was deptuy director psysical security programs department and site responsible for program management and system integration of ashore integrated security systems. Mr. Grubb holds a B.S. degree in industrial engineering from Iowa State Universtiy an M.S. degree in industrial engineering from Purdue University and has copleted the course work (Dec.'96 for a master's degree in public and environment affairs at Indiana University-Purdue Univeristy Indianapolis. Dr. Alfred Skolnick operates System Science Consultants (SSC) specilizing in strategic planning technical program definiton technology assessment and engineering analyses on selected matters of national interest. He has taught physics mathematics and management sciences at University of Virginia and Marymount University and is currently adjunct professor of mathematics at Northern Virginia Community College. Form 1985 to 1989 he was president of the American Society of Noval Engineers. Dr. Skolnick served at Applied Physic

In an era of fiscal austerity, downsizing and unforgiving pressure upon human and economic capital, it is an Augean task to identify resources for fresh and creative work. The realities of the day and the practical demands of more immediate fleet needs can often dictate higher priorities. Yet, the Navy must avoid eating its seed corn. Exercising both technical insight and management foresight, the fleet, the R&D community, the Office of the Chief of Naval Operations (OpNav) and the product engineering expertise of the Naval Surface Warfare Center (NSWC) are joined and underway with integrated efforts to marry new, fully demonstrated technologies and operational urgencies. Defense funding today cannot sponsor all work that can be mission-justified over the long term because budgets are insufficient to support product maturation within the classical development cycle. However, by rigorous technical filtering and astute engineering of both marketplace capabilities and currently available components, it is possible in a few select cases to compress and, in effect, integrate advanced development (6.3), engineering development (6.4), weapon procurement (WPN), ship construction (SCN), operation and maintenance (O&M,N) budgetary categories when fleet criticalities and technology opportunities can happily meet. In short, 6.3 funds can be applied directly to ''ripe gateways'' so modern technology is inserted into existing troubled or aging systems, sidestepping the lengthy, traditional development cycle and accelerating practical payoffs to recurrent fleet problems. To produce such constructive results has required a remarkable convergence of sponsor prescience and engineering workforce excellence. The paper describes, extensively, the philosophy of approach, transition strategy, polling of fleet needs, technology assessment, and management team requirements. The process for culling and selecting specific candidate tasks for SHARP sponsorship (matching operational need with t

关键词： Naval vessels

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An improved ASIC design and implementation for color space conversion applications

An improved ASIC design and implementation for color space c...

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Midwest Symposium on Circuits and systems (MWSCAS)

作者： M. Nsour H.S. Abdel-Aty-Zohdy Microelectronics System Design Laboratory Department of Electrical and Systems Engineering Oakland University Rochester MI USA

The design and VLSI implementation of an ASIC chip, which performs real time conversion, the Red, Green, and Blue (RGB) color coordinates to CIE (Commission Internationale de l'Eclairage) standard L* (luminance), a* (redness-greenness), and b* (yellowness-blueness) color coordinates, is presented. High-speed operation of this ASIC is achieved by pipelining the input data, and performing parallel operations. The ASIC is implemented using CMOS, 2.0 /spl mu/m, n-well process. It occupies an area of 1.55/spl times/1.45 mm/sup 2/. The chip is intended to be used in colorimetry manufacturing inspection and robotics precision. Inputs are 3 bits each. a* and b* are 7 bits each, L* is 6 bits.

关键词： Application specific integrated circuits systems engineering and theory Inspection Application software Humans Extraterrestrial measurements Instruments Color microelectronics Laboratories

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The Flexible Hypercube: A New Topology Suitable for Use in Metropolitan Area Networks

The Flexible Hypercube: A New Topology Suitable for Use in M...

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IEEE Workshop on Local and Metropolitan Area Networks (LANMAN)

作者： T. Hameenanttila Xin-Li Guan J.D. Carothers Jian-Xin Chen The University of Arizona Computer Systems Design Laboratory Department of Electrical and Computer Engineering University of Arizona Tucson Tucson AZ USA

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A BIST SCHEME FOR A SNR, GAIN TRACKING, AND FREQUENCY-RESPONSE TEST OF A SIGMA-DELTA ADC

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IEEE TRANSACTIONS ON CIRCUITS AND systems II-ANALOG AND DIGITAL SIGNAL PROCESSING 1995年第1期42卷 1-15页

作者： TONER, MF ROBERTS, GW Department of Electrical Engineering Microelectronics and Computer Systems Laboratory McGill University Montreal Canada

Built-in-self test (BIST) for VLSI systems is desirable in order to reduce the cost per chip of production-time testing by the manufacturer, In addition, it can provide the means to perform in-the-held diagnostics, This paper discusses a mixed analog-digital BIST (MADBIST) for a signal-to-noise-ratio test, gain tracking test, and frequency response test of a Sigma-Delta analog-to-digital converter, The MADBIST strategy for the SNR, GT, and FR tests of the ADC is introduced, accuracy issues are discussed, and experimental results are presented.

关键词： Built-in self-test Frequency response System testing Analog-digital conversion Very large scale integration Costs Manufacturing Signal to noise ratio Delta-sigma modulation Group technology

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An algorithm for the design of a residue-to-binary converter

An algorithm for the design of a residue-to-binary converter

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Midwest Symposium on Circuits and systems (MWSCAS)

作者： A.A. Hiasat H.S. Abdel-Aty-Zohdy Microelectronics System Design Laboratory Department of Electrical and Systems Engineering Oakland University Rochester MI USA

This paper presents a new algorithm which converts moduli (2/sup k/, 2/sup k/-1, 2/sup k/-1-1) residue numbers to their binary equivalents. A suitable hardware implementation which utilizes binary adders, and needing no memory, is proposed. If the system is pipelined, then the throughput rate is that of a single (3k-1) bits adder. Thus, hardware requirements and execution time are less, with corresponding larger dynamic range.

关键词： Algorithm design and analysis Signal processing algorithms Hardware Equations microelectronics Laboratories design engineering systems engineering and theory Throughput Adders

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Arbitrary-precision signal generation for bandlimited mixed-signal testing

Arbitrary-precision signal generation for bandlimited mixed-...

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IEEE International Test Conference

作者： X. Haurie G.W. Roberts Microelectronics and Computer Systems Laboratory Department of Electrical Engineering McGill University Montreal QUE Canada

This paper presents significant improvements in the generation of analog signals for on-chip analog circuit testing. In particular the novel oscillators proposed here can achieve signal-to-noise ratios far greater than previous designs, while remaining area-efficient. One particular example illustrates a 30 dB improvement in the SNR. Alternatively, signals can be generated with the same SNR as with older designs but over a wider range of frequencies. Multitone signal generation is enhanced in the same fashion. Prototypes were built and satisfactorily tested on FPGA technology.

关键词： Signal generators Circuit testing Oscillators Frequency Hardware Signal to noise ratio Costs Delta modulation Circuit noise Noise generators

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