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TECHNICAL ISSUES REGARDING SATELLITE PACKET-SWITCHING

INTERNATIONAL JOURNAL OF SATELLITE COMMUNICATIONS 1994年第3期12卷 257-267页

作者： IVANCIC, WD CHU, P SHYY, DJ National Aeronautics and Space Administration Lewis Research Center Cleveland Ohio 44135 USA. A design engineer in the Digital Technology Branch of the Space Electronics Division. He has extensive experience in satellite communications systems modulation and coding on-board switching and routeing and high speed digital design. Since joining NASA in 1982 Mr. Ivancic has been responsible for the development of a variety of matrix switch controllers ground terminal equipment numerous pieces of special test equipment a beacon controller for the SARSAT program (Search and Rescue Satellite) and a time-shared decoder for a processing satellite. In addition Mr. Ivancic has been technical contract monitor on a number of advanced communications technology contracts including the Advanced Modulation Technology Development a 5 GHz fibre-optic link and multi-programmable modem study. He was awarded the B.S.E.E. and M.S.E.E. degrees by Cleveland State University in 1982 and 1986 respectively. Cleveland State University Cleveland Ohio 44115 USA. Currently an assistant professor of Electrical Engineering Department at Cleveland State University. He obtained the M.S. and Ph.D. degrees from Iowa State University majoring in Electrical and Computer Engineering. His research interests include high-speed computer networks digital systems and neural networks applications. He is a member of Sigma Xi Phi Kappa Phi as well as the IEEE and ACM. ComSearch Reston Virginia 22091 USA. Received the B.S. degree in electrical engineering from National Chiao-Tung University Hsin-Chu Taiwan in 1983 and the M.S. and Ph.D. degrees in electrical engineering from Georgia Institute of Technology Atlanta GA in 1986 and 1990 respectively. From June 1987 to October 1987 he worked for the Department of Neurology Emory University Atlanta as a Programmer. From September 1989 to December 1989 he worked for the Advanced Development Laboratory. AMP Inc. Atlanta as a Test Engineer. From February 1990 to August 1993 he wor

Many concepts for advanced communication satellite networks have recently been proposed. Critical technical issues relating to satellite packet switching for meshed very small aperture terminal networks and broadband ... 详细信息

关键词： FAST PACKET SWITCH BISDN MESHED VSAT ON-BOARD PROCESSING

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PROCESS-DEPENDENT CIRCUIT MODELING AND SIMULATION OF SOIJFETS - DIGITAL VLSI APPLICATIONS

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SIMULATION 1993年第2期60卷 113-126页

作者： ABDELATYZOHDY, HS TALKHAN, IE [o_1]Microelectronics Systems Design Laboratory Department of Electrical and Systems Engineering Oakland University Rochester Michigan 48309-4401 [o_2]Microelectronics Systems Design Laboratory Department of Electrical and Systems Engineering Oakland University Rochester Michigan 48309-4401

Accurate circuit modeling and simulation of Silicon-on-Insulator (SOI) enhancement and depletion Junction Field-Effect transistors (JFETs) is presented. The nonuniformity in FET device parameters along the channel depth (due to fabrication processes), is taken into account. This is typical in SOI and other thin-film structures. Since SOI fabrication processes parameters are represented, in our model, by a closed form nobility variation, improved model accuracy is guaranteed. Simulation results are found to be within less than 3% of actual measurements. Small-signal circuit-model parameters are determined for SOI FJETs and then evaluated for further logic applications. Inverters with a channel Enhancement-JFET (E-JFET) drivers and n-channel depletion-JFET loads (E/D inverters) are also considered with different supply voltage values, device parameters and digital applications.

关键词： PROCESS-DEPENDENT CIRCUIT MODELING AND SIMULATION THIN FILM SILICON-ON INSULATOR JUNCTION FIELD EFFECT TRANSISTORS VLSI LOGIC CIRCUITS ENHANCEMENT-JFETS

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VLSI implementation of a feature mapping neural network

VLSI implementation of a feature mapping neural network

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Midwest Symposium on Circuits and systems (MWSCAS)

作者： E.T. Carlen H.S. Abdel-Aty-Zohdy Microelectronics Systems Design Laboratory Department of Electrical and Systems Engineering Oakland University Rochester MI USA

Modification of Kohonen's self-organizing feature map algorithm and its dedicated parallel hardware implementation are the focus of this paper. This work is motivated by the need to implement a 5/spl times/5 neural network using digital standard cells and high level VLSI system design tools. The neural net considered is a two layered, feed forward architecture that learns relationships among unknown input data patterns. The prototype system consists of 25 processing units (neurons). Each processing unit operates at 10 MHz. Communication among processing units is accomplished using a broadcast bus. Performance of the system is estimated to be 110,000 iterations per second.< >

关键词： Very large scale integration Neural networks Unsupervised learning Image coding computer architecture microelectronics Laboratories design engineering systems engineering and theory Focusing

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A BIST scheme for an SNR test of a sigma-delta ADC

A BIST scheme for an SNR test of a sigma-delta ADC

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IEEE International Test Conference

作者： M.F. Toner G.W. Roberts Microelectronics and Computer Systems Laboratory Department of Electrical Engineering McGill University Montreal Canada

Built-In-Self-Test (BIST) for VLSI systems is desirable in order to reduce the cost per chip of production-time testing by the manufacturer. In addition, it can provide the means to perform in-the-field diagnostics. This paper discusses a mixed analog-digital BIST (MADBIST) for a signal-to-noise-ratio test of an analog-to-digital converter. The MAD-BIST strategy for the SNR test of the A/D converter is introduced, accuracy issues are discussed, and experimental results are presented.< >

关键词： Built-in self-test Delta-sigma modulation Circuit testing Integrated circuit testing Costs Analog-digital conversion System testing Signal to noise ratio Test equipment Filters

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A 5th order bilinear switched-current Chebyshev filter

A 5th order bilinear switched-current Chebyshev filter

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IEEE International Symposium on Circuits and systems (ISCAS)

作者： I. Song G.W. Roberts Microelectronics and Computer Systems Laboratory Department of Electrical Engineering McGill University Montreal Canada

The design and implementation results of a fifth-order Chebychev filter using switched-current or (SI) bilinear integrators are presented. The signal-flow graph of the filter is derived from an LC ladder and is composed of basic building blocks of bilinear integrators. These bilinear integrators are implemented using an SI integrator. Using a 1.2-/spl mu/m CMOS4S process, simulation results of the bilinear integrator as well as the filter using CADENCE are shown, both at the schematic level and the layout level.< >

关键词： Chebyshev approximation Filters Transfer functions Frequency microelectronics Telecommunication switching Flow graphs Signal processing Switched capacitor circuits CMOS process

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A high-quality analog oscillator using oversampling D/A conversion techniques

A high-quality analog oscillator using oversampling D/A conv...

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IEEE International Symposium on Circuits and systems (ISCAS)

作者： A.K. Lu G.W. Roberts D.A. Johns Microelectronics and Computer Systems Laboratory Department of Electrical Engineering McGill University Montreal QUE Canada Department of Electrical Engineering University of Toronto Toronto ON Canada

A high-quality analog oscillator designed specifically for audio applications is described. Except for a rather imprecise low-pass filter and a 1-b digital-analog converter, the proposed circuit is entirely digital, providing accurate control over its oscillation frequency and amplitude. Experimental results indicate an effective dynamic range of approximately 70 dB, equaling the behavior of a Hewlett-Packard HP3254A high-performance signal generator.< >

关键词： Oscillators Circuits Frequency Digital filters Equations Capacitors Inductors Delta-sigma modulation IIR filters Resonator filters

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A component-invariant second-order switched-current sigma-delta modulator

A component-invariant second-order switched-current sigma-de...

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1992 IEEE International Symposium on Circuits and systems, ISCAS 1992

作者： Crawley, Philip J. Roberts, Gordon W. Microelectronics and Computer Systems Laboratory Department of Electrical Engineering McGill University India

ISBN: (纸本)0780305930

This paper presents the building blocks and design procedure necessary for creating a component-invariant second-order Switched Current (SI) Sigma-Delta Modulator (Σ M). A novel SI second-order integrator block is paramount to the design. A voice-band (4 kHz) A/D converter was designed and laid out in Northern Telecom's 1.2 μm CMOS process. Final transistor level simulations on the netlist derived directly from the layout indicated a resolution of only 10 bits, a result of excessive charge injection and clock feedthrough. © 1992 IEEE.

关键词： Modulators

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Switched-current sigma-delta modulation for A/D conversion

Switched-current sigma-delta modulation for A/D conversion

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1992 IEEE International Symposium on Circuits and systems, ISCAS 1992

作者： Crawley, Philip J. Roberts, Gordon W. Microelectronics and Computer Systems Laboratory Department of Electrical Engineering McGill University India

ISBN: (纸本)0780305930

This paper presents the design of a switched-current (SI) Double-Integrator Sigma-Delta Modulator (DISDM) for A/D conversion that is intended for voice-band (4kHz) telecommunication applications. With the creation of several new SI signal processing building blocks, a SI DISDM has been designed and laid out in Northern Telecom's 1.2 μm CMOS process having an area of 0.5 mm3 and a predicted power consumption of 2.5 mW. Transistor level simulation (SPICE) of the SI DISDM design shows that the circuit performs reasonable well, rating it at 12-bits of linear resolution. In comparisons with corresponding switched-capacitor DISDM designs, the SI version provides a dramatic reduction in both power and area requirements. But, more importantly, the SI design does not utilize linear capacitors and can be fabricated using a standard digital CMOS process. © 1992 IEEE.

关键词： Delta sigma modulation

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HISTOGRAM-BASED DISTORTION AND GAIN TRACKING TESTING OF AN 8-BIT PCM MIXED ANALOG-DIGITAL IC CHIP 35

HISTOGRAM-BASED DISTORTION AND GAIN TRACKING TESTING OF AN 8...

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35TH MIDWEST SYMP ON CIRCUITS AND systems

作者： TONER, MF ROBERTS, GW Microelectronics and Computer Systems Laboratory Department of Electrical Engineering McGill University 3480 University Street Montreal H3A 2A7 Canada

ISBN: (纸本)0780305108

The effective number of bits of a linear Analog-to-Digital Converter (ADC) can be computed using the code density histogram method. In this article, the technique is adapted to test an oversampling or Sigma-Delta (ΣΔ) converter. It is assumed that the device under test includes a ΣΔ modulator, a decimator, and a μ-law compressor. The analog stimulus to the device under test is supplied by a precision signal generator, and the code density histogram of the 8-bit μ-law compressed output of the ADC is analyzed to determine whether the converter is performing within its specifications. This paper presents simulation results which were obtained using a very simple model for the ADC and additive white Gaussian noise. © 1992 IEEE.

关键词： Timing circuits

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Built-in self-diagnostic by space-time compression of test responses

Built-in self-diagnostic by space-time compression of test r...

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1992 IEEE VLSI Test Symposium, VLSI 1992

作者： Karpovsky, M.G. Chaudhry, S.M. Research Laboratory of Design and Testing of Computer Hardware Department of Electrical Computer and Systems Engineering Boston University BostonMA02215 United States

ISBN: (纸本)0780306236

Presents two different methodologies for built-in self-diagnostic of boards and systems by space-time compression of test responses. The first method, soft decision, uses nonbinary multiple error-correcting codes to obtain space-time signatures. These obtained signatures and the corresponding precomputed references are compared and magnitudes of distortions in signatures are analyzed to identify faulty components. The second method, hard decision, makes use of the information indicating whether the corresponding signatures are distorted or not. Both approaches show considerable savings in hardware overheads when compared with a straightforward approach where a separate signature is required for every component. A transition from the soft to hard decision approach results in an increase in the number of signatures required for diagnostic but at the same time it results in a decrease in the complexity of a fault locating algorithm. Results pertaining to VLSI implementations are presented where the hardware overhead is estimated in terms of two-input equivalent gates. © 1992 IEEE.

关键词： Data compression

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