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Prior-Boosted GRL: Microarchitecture design Space Exploration via Graph Representation Learning

IEEE Transactions on Computer-Aided design of Integrated Circuits and systems 2025年第3期44卷 1141-1154页

作者： Wu, Zheng Shen, Jinyi Yi, Xiaoling Shang, Li Yang, Fan Zeng, Xuan Fudan University State Key Laboratory of Integrated Circuits and Systems The School of Microelectronics Shanghai200433 China Fudan University State Key Laboratory of Integrated Circuits and Systems Shanghai200433 China KU Leuven Department of Electrical Engineering Microelectronics Circuits and Systems Leuven3000 Belgium Fudan University State Key Laboratory of Integrated Circuits and Systems The School of Computer Science Shanghai200433 China

The design space exploration (DSE) of contemporary microprocessors faces a significant challenge of high-computational cost. In this context, we introduce Prior-boosted graph representation learning (GRL), a novel framework for the DSE of the microarchitectures the microprocessors underpinned by graph embeddings. Using GRL, Prior-boosted GRL constructs a compact and continuous vector space for design representation. This framework is further boosted by an efficient sampling algorithm informed by prior knowledge, which is instrumental in generating a superior set of initial designs to accelerate the exploration process. A well-designed ensemble surrogate model is combined with the multiobjective Bayesian optimization to explore the design space holistically within this graph-embedding domain. Rigorous experimental evaluations conducted on the RISC-V Berkeley-Out-of-Order Machine (BOOM) platform demonstrate that Prior-boosted GRL substantially surpasses preceding methods, achieving a 107.79% enhancement in Pareto front quality compared to the state-of-the-art DSE algorithm. It also outstrips manual designs on performance, power, and area metrics. As of this writing, Prior-boosted GRL holds the first place in the ICCAD 2022 CAD Contest evaluation platform. © 2024 IEEE.

关键词： Graph embeddings

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ATOM: An Automatic Topology Synthesis Framework for Operational Amplifiers

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IEEE Transactions on Computer-Aided design of Integrated Circuits and systems 2025年第3期44卷 1193-1198页

作者： Shen, Jinyi Yang, Fan Shang, Li Yan, Changhao Bi, Zhaori Zhou, Dian Zeng, Xuan Fudan University State Key Laboratory of Integrated Chips and Systems School of Microelectronics Shanghai200433 China Fudan University State Key Laboratory of Integrated Chips and Systems The School of Computer Science Shanghai200433 China Fudan University State Key Laboratory of Integrated Chips and Systems Microelectronics Department Shanghai200433 China University of Texas at Dallas Department of Electrical Engineering DallasTX75080 United States

Bayesian optimization (BO) is more efficient in automatically synthesizing operational amplifier (opamp) topologies compared to conventional methods. However, the design space for behavior-level opamp topologies involves numerous connections that are difficult to comprehend, and evaluating each topology incurs substantial computational costs. To tackle these challenges, this brief introduces ATOM, an automatic opamp topology synthesis framework. We construct a concise design space for behavior-level opamp topologies, consisting of topologies that designers can easily understand. We propose an opamp topology optimization method that incorporates freeze-thaw BO. This method efficiently explores the design space and expedites the evaluation process. Experimental studies demonstrate that ATOM outperforms state-of-the-art topology synthesis methods in terms of success rate and optimization results while reducing the number of required simulations by up to 8.15 times. The source code for ATOM is available at https://***/Jinyi-Shen/ATOM. © 2024 IEEE.

关键词： Thawing

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Revisiting sensitivity-based analog sizing with derivative-aware Bayesian optimization and error-suppressed adjoint analysis 24

Revisiting sensitivity-based analog sizing with derivative-a...

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43rd International Conference on Computer-Aided design, ICCAD 2024

作者： Lyu, Ruiyu Zhao, Aidong Meng, Yuan Zhu, Keren Bi, Zhaori Yan, Changhao Yang, Fan Zhou, Dian Zeng, Xuan State Key Laboratory of Integrated Chips and Systems School of Microelectronics Fudan University Shanghai China Department of Electrical Engineering University of Texas at Dallas RichardsonTX United States

ISBN: (纸本)9798400710773

Current state-of-the-art (SOTA) analog circuit sizing methods predominantly rely on derivative-free algorithms. However, these methods struggle with sample efficiency due to the lack of derivative information, acting as a bottleneck for further advancements. In contrast, classic sensitivity analysis computes partial derivatives of circuit performance with respect to design parameters, enabling efficient first-order optimization. Yet, sensitivity-driven analog sizing has seen limited use due to: 1) accumulated numerical errors from nonlinear devices, and 2) the complex, non-convex nature of circuit optimization problems, which makes local search methods like gradient descent ineffective for global optimization. To address these challenges, this paper equips SOTA analog sizing algorithms with derivative awareness and proposes DarBO, a Derivative-aware Bayesian Optimization method. DarBO uses derivatives from error-suppressed adjoint sensitivity analysis to improve Gaussian process posteriors in local optimization, enhancing convergence with fewer circuit simulations. For global exploration, DarBO adapts a derivative-aware Gaussian mixture model (d-GMM) for region partitioning and a gradient-driven Monte Carlo tree search (d-MCTS) for subregion selection. By bridging classic sensitivity-driven analog sizing with SOTA Bayesian optimization algorithms, DarBO offers an efficient and robust solution for analog circuit sizing. Experimental results show that DarBO achieves up to 5.0 × acceleration in terms of the number of circuit simulations compared to existing first-order and derivative-free optimization methods. © 2024 Copyright is held by the owner/author(s).

关键词： Convex optimization

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Improving the ductility of laser directed energy deposited borated stainless steel by increasing laser power

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Journal of Manufacturing Processes 2025年 145卷 494-507页

作者： Huang, Sheng Li, Qingyu Zhang, Xiaoyu Cui, Bin Li, Dichen Zhang, Anfeng Miao, Kai State Key Laboratory for Manufacturing Systems Engineering School of Mechanical Engineering Xi'an Jiaotong University Xi'an710049 China Science and Technology on Reactor System Design Technology Laboratory Nuclear Power Institute of China Chengdu610213 China Department of Mechanical and Electrical Engineering Yuncheng University Yuncheng044000 China Co. Ltd. Chengdu610091 China

Borated stainless steels (BSSs) are extensively applied in the nuclear energy industry due to boron's excellent thermal neutron absorption capacity, but large and brittle borides formed during casting result in a low ductility. Here, a BSS was produced by laser directed energy deposition, and an investigation was conducted to analyze the impact of laser power on both the microstructure and mechanical properties of the deposited material. Fibrous borides with relatively low volume fraction in the overlapping zone resulted in higher ductility, while lamellar borides with relatively large volume fraction in the non-overlapping zone led to higher strength. As the laser power increased from 180 W to 330 W, the size of fibrous and lamellar eutectic borides and austenite increased significantly, the width of the soft overlapping zone increased by 2.27 times, and the elongation increased by 2.03 times, although yield strength and ultimate tensile strength decreased by 46.3 % and 31.7 %, respectively. As a result, these findings confirmed the feasibility of significantly improving the ductility of the as-deposited BSS by increasing the laser power. The work here provides a way to tailoring the mechanical properties of BSS produced by laser additive manufacturing. © 2025 The Society of Manufacturing Engineers

关键词： Ductility

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Age of Information in Internet of Vehicles: A Discrete-Time Multisource Queueing Model

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IEEE Transactions on Communications 2025年第5期73卷 3298-3317页

作者： Zhang, Tianci Chen, Zhengchuan Tian, Zhong Wang, Min Zhen, Li Wu, Dapeng Oliver Li, Yonghui Quek, Tony Q. S. Chongqing University School of Microelectronics and Communication Engineering Chongqing400044 China Shaanxi Key Laboratory of Information Communication Network and Security Xi’an University of Posts and Telecommunications Xi’an710122 China Chongqing University of Posts and Telecommunications School of Optoelectronics Engineering Chongqing400065 China City University of Hong Kong Department of Computer Science Hong Kong The University of Sydney School of Electrical and Information Engineering SydneyNSW2050 Australia Singapore University of Technology and Design Department of Information Systems Technology and Design Tampines 487372 Singapore Yonsei University Yonsei Frontier Laboratory Seoul03722 Korea Republic of

This work studies information freshness of a V2I status updating link in IoV. The status updating link is modeled as a multi-source Ber/Geo/1/1 non-preemptive or preemptive queue. We focus on statistical characteristics of the age of information (AoI) and peak AoI (PAoI). To fully track the AoI evolutions under non-preemptive and preemptive policies, Markov three-dimensional age process (3DAP) and two-dimensional age process (2DAP) are respectively introduced. Their first element is the AoI process;The second one stands for if an update of the concerned source is in transmission and its current age;The third element of 3DAP denotes if an update of another source is in transmission. An analytical approach for studying the AoIs and PAoIs in discrete-time multi-source systems is presented. By studying the state transitions, balance equations, and stationary distributions of 3DAP and 2DAP, analytical expressions of the distributions and averages of AoIs and PAoIs under both queueing policies are derived. Moreover, the optimal probabilistic update selection mechanism (PUSM) that maximizes overall freshness is derived in closed-form for the two-source case. Numerical results validate effectiveness of the theoretical analyses and reveal usefulness of the retransmission. It is found that in terms of improving the overall freshness, the PUSM should be designed to make effective update generation probabilities of sources as close as possible. © 1972-2012 IEEE.

关键词： Queueing theory

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Fully-Standard-Cell-Based Synthesizable Charge-Redistribution SAR ADCs and P&R-Based Layout Automation Framework

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IEEE Access 2025年 13卷 83450-83469页

作者： Li, Shuowei Duran, Ckristian Takenaka, Ritaro Iizuka, Tetsuya The University of Tokyo School of Engineering Department of Electrical Engineering and Information Systems Tokyo 113-0032 Japan The University of Tokyo Systems Design Laboratory School of Engineering Tokyo 113-0032 Japan

This paper presents two fully standard-cell-based synthesizable Successive Approximation Register Analog-to-Digital Converters (SAR ADCs) and the automated layout generation framework. The 1^st design is an 8-bit charge-redistribution SAR ADC. A 4-inverter-cell-based analog switch is proposed, effectively mitigating charge injection/absorption in the capacitive digital-to-analog converter. This prototype is fabricated in a 65nm CMOS process and occupies 0.095mm². With a Nyquist input, the ADC achieves 55.8dB spurious-free dynamic range (SFDR) and 47.7dB signal-to-noise-and-distortion ratio (SNDR) at a sampling frequency of 33.3MS/s without calibration. The power consumption is 0.91mW, achieving Walden Figure of Merit (FoM_W) of 0.13pJ/conversion-step. The 2^nd design is a 12-bit 2-stage pipelined SAR ADC, where a standard-cell-based amplifier is proposed to amplify the residue voltage after the 1^st-stage conversion. This prototype is fabricated also in a 65nm process and occupies 0.136mm². With a Nyquist input, the pipelined ADC achieves 72.1 dB SFDR and 63.1 dB SNDR at a sampling frequency of 22.2MS/s with a simple foreground calibration of the inter-stage amplifier gain. The power consumption is 2.7mW, yielding a FoMW of 0.105pJ/conversion-step. A layout automation framework based on placement and routing (P&R) tool for the standard-cell-based ADCs is proposed and demonstrated with the 8-bit SAR ADC design as an example. © 2013 IEEE.

关键词： Amplifier capacitor charge redistribution layout automation pipelined SAR ADC standard cell switch synthesizable

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ACDV: Adaptive Content Delivery for Vehicular Digital Twin Networks

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IEEE Transactions on Vehicular Technology 2025年第5期74卷 7084-7098页

作者： Zheng, Jinkai Luan, Tom H. Li, Guanjie Yin, Zhisheng Wu, Yuan Dong, Mianxiong Dongguan University of Technology School of Electrical Engineering and Intelligentization Dongguan523808 China Xi'an Jiaotong University School of Cyber Science and Engineering Xi'an710049 China Xidian University School of Cyber Engineering Xi'an710071 China Singapore University of Technology and Design Information Systems Technology and Design Pillar 487372 Singapore Xidian University State Key Laboratory of Isn Xi'an710071 China University of Macau State Key Laboratory of Internet of Things for Smart City 999078 China University of Macau Department of Computer Information Science 999078 China Muroran Institute of Technology Department of Sciences and Informatics Muroran05-08585 Japan

Digital Twins (DTs), serving personalized cloud-based digital assistants, hold great promise for supporting infotainment applications of the Internet of Vehicles (IoVs), in which personalized content such as high-definition maps, system updates, and social video streaming can be delivered from individualized DTs to vehicular users (VUEs) to enhance the intelligence of IoV services and improve their driving experience. This paper proposes a novel content caching framework tailored to DT-enabled IoVs, where DTs selectively cache on-demand contents on edge devices (i.e., cellular base stations and roadside units) managed by the edge service manager (ESM) along the VUE's trip to avoid backbone congestion yet save download time. However, ESMs are inherently selfish and reluctant to contribute resources to cache contents without benefits. Furthermore, considering the diverse trajectories of vehicles, it is inefficient to cache data along a single path. To address these challenges, we propose ACDV, which first models the interactions between the ESMs and DTs as a Stackelberg game to incentivize ESMs to actively participate in the content caching process. We then deploy a Markov model to predict the VUE distribution, which enables DTs to cache contents with a focus on predicted trajectories. To save storage costs, we derive an upper bound of content sizes that the VUE can download within a limited network connection time. Considering the lack of network information and users' private utility model in practical scenarios, we further develop a learning-based algorithm to find the optimal pricing scheme and content size strategies of ESMs and DTs. Through extensive simulations, we show that our proposal can effectively find the optimal strategy and achieve a fast convergence speed and high-level performance compared to the baselines. © 1967-2012 IEEE.

关键词： Markov processes

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Exploring Edge-Driven Collaborative Fine-Tuning Toward Customized AIGC Services

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IEEE Network 2025年第3期39卷 293-301页

作者： Zhang, Qinnan Zong, Tianqi Xiong, Zehui Sun, Pangbo Zhu, Jianming Qiu, Wangjie Zheng, Zhiming Poor, H. Vincent Beihang University Institute of Artificial Intelligence Beijing Advanced Innovation Center for Future Blockchain and Privacy Computing Zhongguancun Laboratory Beijing100191 China Singapore University of Technology and Design Information Systems Technology and Design Tampines 487372 Singapore Qingcheng.AI Ltd. Beijing100084 China Central University of Finance and Economics School of Information Beijing100081 China Princeton University Department of Electrical and Computer Engineering PrincetonNJ08544 United States

With the popularization of artificial intelligence-generated content (AIGC), the explosion of end users is spurring an unprecedented diversity in preferences. To cope with this challenge, the AIGC paradigm is shifting from cloud-driven pre-trained large models to edge-driven personalized customization models. The former are large-scale models with more than 100 billion parameters trained based on massive data, while the latter introduce heterogeneous user preferences or professional knowledge to fine-tune the former. However, such fine-tuning incurs costly resource consumption and privacy disclosure. In this paper, we offer a holistic perspective on the AIGC fine-tuning framework spanning from end user to edge to cloud. Specifically, we first investigate how to deploy an edge-driven collaborative fine-tuning task through federated learning. Then, we discuss a verifiable model consensus protocol and fairness incentive design for edge servers to participate in a collaborative learning task. In addition, a case study focuses on the medical scenario, where we develop a practical X-ray diagnostic demo through collaborative fine-tuning of a multimodal pre-training model, and the diagnostic dialogue and performance results are compared. Finally, potential research directions are identified to advance the edge-driven customized AIGC services. © 1986-2012 IEEE.

关键词： Phase change materials

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Chiral microwave nonreciprocity demonstrated via Rayleigh and Sezawa modes supported in an Al0.58Sc0.42N/4H−SiC platform

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Physical Review Applied 2025年第3期23卷 034058-034058页

作者： A.R. Will-Cole Xingyu Du Bin Luo Valeria Lauter Alexander Grutter Lisa Hackett Michael Miller Yuanchen Deng Brandon Smith Microelectronics engineering systems and applications Sandia National Laboratories Albuquerque 87115 NM Department of Electrical and Systems Engineering The University of Pennsylvania Philadelphia Pennsylvania USA Department of Electrical Engineering Northeastern University Boston Massachusetts USA Neutron Sciences Division Oak Ridge National Laboratory Oak Ridge Tennessee 37831 USA NIST Center for Neutron Research National Institute of Standards and Technology Gaithersburg Maryland 20899 USA

Chirality plays a crucial role in the helicity mismatch between surface acoustic waves and magnetic spin waves, leading to nonreciprocal transmission of acoustic power for coupled magnetoacoustic modes. Acoustic modes with both longitudinal and shear strain exhibit elliptical particle displacements, making them chiral, and different acoustic modes can exhibit different helicities of this elliptical particle displacement. Here, we study chiral acoustic modes with different helicities supported on the same piezoelectric platform and their interaction with magnetic spin waves. Our study demonstrates that the nonreciprocal transmission of acoustic power is driven by the helicity mismatch effect and, specifically, that the handedness of the nonreciprocity is based on whether the surface acoustic wave has retrograde (Rayleigh mode) or prograde (Sezawa mode) elliptical particle displacement with respect to the propagation direction. We found the transmission nonreciprocity to be significant, with 7.3 dB/mm for the retrograde particle displacement (Rayleigh mode at 2.358 GHz) and 3.3 dB/mm for prograde particle displacement (Sezawa mode at 3.112 GHz). This work highlights that piezoelectric platforms can be engineered to support acoustic modes with opposite helicities to enable frequency-selective nonreciprocal radiofrequency and microwave components, such as isolators and circulators, through coupled acoustic spin wave interactions.

关键词： Acoustic waves

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Robust Avalanche (1.5 kV, 2 kA/cm2) in Vertical GaN Diodes on Patterned Sapphire Substrate

IEEE Electron Device Letters

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IEEE Electron Device Letters 2025年第5期46卷 717-720页

作者： Wang, Yifan Xiao, Ming Yang, Zineng Porter, Matthew Cheng, Kai Song, Qihao Kravchenko, Ivan Zhang, Yuhao Virginia Tech Center of Power Electronics Systems BlacksburgVA24060 United States Xidian University School of Microelectronics Xi’an710071 China Enkris Semiconductor Inc. Suzhou215123 China Oak Ridge National Laboratory Center for Nanophase Materials Sciences Oak RidgeTN37830 United States Virginia Tech BlacksburgVA24060 United States The University of Hong Kong Department of Electrical and Electronic Engineering Hong Kong Hong Kong

The lack of avalanche capability is a keylimitation of current lateral GaN devices. Despite the reportof avalanche in vertical GaN-on-GaN devices, the high wafercost hinders device commercialization. Here we demon-strate a circuit-level avalanche in vertical GaN diodeson low-cost patterned sapphire substrate (PSS), with theavalanche voltage (1.57 kV) and avalanche current den-sity (>2 kA/cm2) both being the highest reported in GaNdevices on foreign substrates. The PSS enables a lowerdislocation density than conventional sapphire substrateand is employed in high-voltage GaN devices for the firsttime. The avalanche voltage in the circuit test reaches 98%of the parallel-plane limit, further affirming that near-idealavalanche breakdown can be realized on GaN devices onforeign substrates. These results show the promise of theGaN-on-PSS platform for low-cost, robust power devices. © 1980-2012 IEEE.

关键词： III-V semiconductors

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