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A Numerical Method to Analyze Electromagnetic Scattering from Composite Plasmonic Structures Involving a Metal-Metal Interface

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A Numerical Method to Analyze Electromagnetic Scattering fro...

Antennas and Propagation Society International Symposium

作者： Doolos Aibek Uulu Rui Chen Liang Chen Ping Li Hakan Bagci Division of Computer Electrical and Mathematical Science and Engineering King Abdullah University of Science and Technology (KAUST) Thuwal Saudi Arabia Department of Mathematics and Natural Sciences University of Central Asia (UCA) Naryn Kyrgyzstan Key Laboratory of Ministry of Education of Design and Electromagnetic Compatibility of High-Speed Electronic Systems Shanghai Jiao Tong University Shanghai China

A coupled system of volume integral and hydrodynamic equations is formulated to analyze electromagnetic scattering from composite plasmonic structures involving a metal-metal interface. This coupled system in unknowns electric flux and free electron velocity is discretized using Schaubert-Wilton-Glisson basis functions. Inserting these expansions into the coupled system of equations and applying Galerkin testing yield a matrix equation. Two-level iterative scheme is used to solve this matrix equation for the unknown expansion coefficients. To demonstrate the accuracy of the proposed method, numerical results are compared to those obtained using an extended Mie series approach that takes into account the hydrodynamic equation and the boundary conditions it requires.

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Low Power and Temperature-Resilient Compute-In-Memory Based on Subthreshold-FeFET

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arXiv 2023年

作者： Zhou, Yifei Huang, Xuchu Yang, Jianyi Ni, Kai Amrouch, Hussam Zhuo, Cheng Yin, Xunzhao Zhejiang University Hangzhou China Department of Electrical Engineering University of Notre Dame Notre Dame United States AI Processor Design Technical University of Munich TUM School of Computation Information and Technology Munich Institute of Robotics and Machine Intelligence Munich Germany Key Laboratory of Collaborative Sensing and Autonomous Unmanned Systems of Zhejiang Province Hangzhou China

Compute-in-memory (CiM) is a promising solution for addressing the challenges of artificial intelligence (AI) and the Internet of Things (IoT) hardware such as"memory wall" issue. Specifically, CiM employing nonvolatile memory (NVM) devices in a crossbar structure can efficiently accelerate multiply-accumulation (MAC) computation, a crucial operator in neural networks among various AI models. Low power CiM designs are thus highly desired for further energy efficiency optimization on AI models. Ferroelectric FET (FeFET), an emerging device, is attractive for building ultra-low power CiM array due to CMOS compatibility, high ION/IOFF ratio, etc. Recent studies have explored FeFET based CiM designs that achieve low power consumption. Nevertheless, subthreshold-operated FeFETs, where the operating voltages are scaled down to the subthreshold region to reduce array power consumption, are particularly vulnerable to temperature drift, leading to accuracy degradation. To address this challenge, we propose a temperature-resilient 2T-1FeFET CiM design that performs MAC operations reliably at subthreahold region from 0°C to 85°C, while consuming ultra-low power. Benchmarked against the VGG neural network architecture running the CIFAR-10 dataset, the proposed 2T-1FeFET CiM design achieves 89.45% CIFAR-10 test accuracy. Compared to previous FeFET based CiM designs, it exhibits immunity to temperature drift at an 8-bit wordlength scale, and achieves better energy efficiency with 2866 TOPS/W. Copyright © 2023, The Authors. All rights reserved.

关键词： Energy efficiency

Development of an IoT-Based Soil Macronutrient Analysis System Utilizing Electrochemical Sensors and Machine Learning Algorithms

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Development of an IoT-Based Soil Macronutrient Analysis Syst...

Network, Multimedia and Information Technology (NMITCON) International Conference on

作者： Timothy M. Amado Adrian Erwin D. Alvarez Allyssa Ocampo Venise Aziel F. Paz Airah Jan N. Punongbayan Lemuel M Yumena Maria Victoria C. Padilla Gilfred Allen M. Madrigal Lean Karlo S. Tolentino Edmund G. Monilar Electronics Engineering Department Technological University of the Philippines Manila Philippines Center for Engineering Design Fabrication and Innovation College of Engineering Technological University of the Philippines Manila Philippines Intelligent Systems Applications and Circuits Laboratory (ISAAC) Integrated Research and Training Center Technological University of the Philippines Manila Philippines Center for Artificial Intelligence and Nanoelectronics (CAIN) Integrated Research and Training Center Technological University of the Philippines Manila Philippines Department of Electrical Engineering National Sun Yat-sen University Kaohsiung Taiwan

Efficient administration of principal soil nutrients is essential for achieving rational agriculture and minimizing economic losses. To improve on-site observing techniques and soil management, the utilization of advanced sensors capable of quantifying soil properties is crucial. In this study, three sensors were employed: an Ion Sensitive Field Effect Transistor (ISFET) pH sensor, a soil moisture sensor, and an RGB color sensor with an IR filter and white LED (TCS34725). The ISFET pH sensor, functioning as a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), provided pH measurements ranging from 1 to 14 and exhibited temperature resistance between 0 to 100 degrees Celsius. The soil moisture sensor was designed to determine soil moisture content within a range of 0 to 1023. The RGB color sensor, by reducing the infrared spectral component of incoming light, enabled precise color measurements. These sensors were integrated into the Arduino MEGA 2560 microcontroller board to facilitate simultaneous operation of complex schemes. The acquired sensor data were correlated to the concentrations of soil macronutrients, specifically Nitrogen (N), Phosphorus (P), and Potassium (K). Through the implementation of machine learning algorithms, the levels of macronutrients can be determined, and for the training set of these algorithms, data collection was conducted using over 300 soil samples.

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6-bit 1-GS/s Partially Active Flash ADC with Comparator Offset Correction

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6-bit 1-GS/s Partially Active Flash ADC with Comparator Offs...

IEEE International Symposium on Smart Electronic systems (iSES)

作者： Nidhi Sharma Vinayak Hande Rajesh Kumar Srivastava Devarshi Mrinal Das Department of Electrical Engineering Indian Institute of Technology Ropar Rupnagar India Integrated Systems and Circuit Design Carinthia University of Applied Sciences Villach Austria Semi-conductor Laboratory Ministry of Electronics & Information Technology (MeitY) S.A.S Nagar India

ISBN: (纸本)9798350399233

This paper presents a low-power 6-bit 1 GS/s partially active flash analog-to-digital converters (ADC) in 65-nm CMOS technology. A novel comparator offset correction technique is proposed, which does not require additional foreground calibration cycles. The partially active second-stage comparison is employed for power efficiency. A third-stage comparison is introduced for offset correction using fifteen low-offset comparators, out of which two are activated. The 0.5-bit redundancy from the first-stage provides the tolerance to track-and-hold (T/H) buffer settling error for high-speed applications. The simulation results show that the ADC achieves a signal-to-noise and distortion ratio (SNDR) of 36.36 dB and a spurious-free dynamic range (SFDR) of 48.65 dB at a Nyquist frequency of 500 MHz with the power consumption of 13.98 mW.

关键词： Power demand Simulation Termination of employment Dynamic range CMOS technology Distortion Calibration

Topology Optimization of Random Memristors for Input-Aware Dynamic SNN

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arXiv 2024年

作者： Wang, Bo Wang, Shaocong Lin, Ning Li, Yi Yu, Yifei Zhang, Yue Yang, Jichang Wu, Xiaoshan He, Yangu Wang, Songqi Chen, Rui Li, Guoqi Qi, Xiaojuan Wang, Zhongrui Shang, Dashan Department of Electrical and Electronic Engineering The University of Hong Kong Hong Kong ACCESS – AI Chip Center for Emerging Smart Systems InnoHK Centers Hong Kong Science Park Hong Kong Key Lab of Fabrication Technologies for Integrated Circuits Institute of Microelectronics Chinese Academy of Sciences Beijing100029 China Laboratory of Microelectronic Devices & Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing100029 China Key Laboratory of Brain Cognition and Brain-inspired Intelligence Technology Institute of Automation Chinese Academy of Sciences Beijing100190 China University of Chinese Academy of Sciences Beijing100049 China

There is unprecedented development in machine learning, exemplified by recent large language models (GPT4) and world simulators (SORA), which are artificial neural networks (ANNs) running on digital computers. However, they still cannot parallel human brains in terms of energy efficiency and the streamlined adaptability to inputs of different difficulties, due to differences in signal representation, optimization, run-time reconfigurability, and hardware architecture. To address these fundamental challenges, we introduce pruning optimization for input-aware dynamic memristive spiking neural network (PRIME). Signal representation-wise, PRIME employs leaky integrate-and-fire neurons to emulate the brain’s inherent spiking mechanism. Drawing inspiration from the brain’s structural plasticity, PRIME optimizes the topology of a random memristive SNN, without expensive memristor conductance fine-tuning. For runtime reconfigurability, inspired by the brain’s dynamic adjustment of computational depth, PRIME employs an input-aware dynamic early stop policy to minimize latency during inference, thereby boosting energy efficiency without compromising performance. Architecture-wise, PRIME leverages memristive in-memory computing, mirroring the brain and mitigating the von Neumann bottleneck. We validated our system using a 40 nm 256 Kb memristor-based in-memory computing macro on neuromorphic image classification and image inpainting. Our results demonstrate the classification accuracy and Inception Score (IS) are comparable to the software baseline, while achieving 37.83× and 62.50× improvements in energy efficiency. Furthermore, we attained 77.0% and 12.5% computational load savings with minimal reduction in performance. The system also exhibits robustness against stochastic synaptic noise of analogue memristors. Our software-hardware co-designed model paves the way to future brain-inspired neuromorphic computing of brain-like energy efficiency and adaptivity. Copyright © 202

关键词： Memristors

The Age of Generative AI and AI-Generated Everything

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arXiv 2023年

作者： Du, Hongyang Niyato, Dusit Kang, Jiawen Xiong, Zehui Zhang, Ping Cui, Shuguang Shen, Xuemin Mao, Shiwen Han, Zhu Jamalipour, Abbas Vincent Poor, H. Kim, Dong In School of Computer Science and Engineering Nanyang Technological University Singapore639798 Singapore School of Automation Guangdong University of Technology Key Laboratory of Intelligent Information Processing and System Integration of IoT Ministry of Education Guangzhou510006 China Guangdong-HongKong-Macao Joint Laboratory for Smart Discrete Manufacturing Guangzhou510006 China Pillar of Information Systems Technology and Design Singapore University of Technology and Design Singapore487372 Singapore State Key Laboratory of Networking and Switching Technology Beijing University of Posts and Telecommunications China Chinese University of Hong Kong Shenzhen China Department of Electrical and Computer Engineering University of Waterloo WaterlooONN2L 3G1 Canada Department of Electrical and Computer Engineering Auburn University AuburnAL36849-5201 United States Department of Electrical and Computer Engineering University of Houston HoustonTX77004 United States Department of Computer Science and Engineering Kyung Hee University Seoul446-701 Korea Republic of School of Electrical and Information Engineering University of Sydney SydneyNSW2006 Australia Department of Electrical and Computer Engineering Princeton University PrincetonNJ08544 United States Department of Electrical and Computer Engineering Sungkyunkwan University Suwon16419 Korea Republic of

Generative AI (GAI) has emerged as a significant advancement in artificial intelligence, renowned for its language and image generation capabilities. This paper presents "AIGenerated Everything" (AIGX), a concept that extends GAI beyond mere content creation to real-time adaptation and control across diverse technological domains. In networking, AIGX collaborates closely with physical, data link, network, and application layers to enhance real-time network management that responds to various system and service settings as well as application and user requirements. Networks, in return, serve as crucial components in further AIGX capability optimization through the AIGX lifecycle, i.e., data collection, distributed pre-training, and rapid decision-making, thereby establishing a mutually enhancing interplay. Moreover, we offer an in-depth case study focused on power allocation to illustrate the interdependence between AIGX and networking systems. Through this exploration, the article analyzes the significant role of GAI for networking, clarifies the ways networks augment AIGX functionalities, and underscores the virtuous interactive cycle they form. This article paves the way for subsequent future research aimed at fully unlocking the potential of GAI and networks. © 2023, CC BY.

关键词： Decision making

Low Power and Temperature- Resilient Compute-In-Memory Based on Subthreshold-FeFET

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Low Power and Temperature- Resilient Compute-In-Memory Based...

design, Automation and Test in Europe Conference and Exhibition

作者： Yifei Zhou Xuchu Huang Jianyi Yang Kai Ni Hussam Amrouch Cheng Zhuo Xunzhao Yin Zhejiang University Hangzhou China ZJU - Hangzhou Global Scientific and Technological Innovation Center Hangzhou China Department of Electrical Engineering University of Notre Dame Notre Dame USA Chair of AI Processor Design Technical University of Munich TUM School of Computation Information and Technology Munich Institute of Robotics and Machine Intelligence Munich Germany Key Laboratory of Collaborative Sensing and Autonomous Unmanned Systems of Zhejiang Province Hangzhou China

ISBN: (数字)9783981926385

ISBN: (纸本)9798350348606

Compute-in-memory (CiM) is a promising solution for addressing the challenges of artificial intelligence (AI) and the Internet of Things (IoT) hardware such as “memory wall” issue. Specifically, CiM employing nonvolatile memory (NVM) devices in a crossbar structure can efficiently accelerate multiply-accumulation (MAC) computation, a crucial operator in neural networks among various AI models. Low power CiM designs are thus highly desired for further energy efficiency optimization on AI models. Ferroelectric FET (FeFET), an emerging device, is attractive for building ultra-low power CiM array due to CMOS compatibility, high ION / $I$ O F F ratio, etc. Recent studies have explored FeFET based CiM designs that achieve low power consumption. Nevertheless, subthreshold-operated FeFETs, where the operating voltages are scaled down to the subthreshold region to reduce array power consumption, are particularly vulnerable to temperature drift, leading to accuracy degradation. To address this challenge, we propose a temperature-resilient 2T-1FeFET CiM design that performs MAC operations reliably at subthreahold region from 0°C to 85°C, while consuming ultra-low power. Benchmarked against the VGG neural network architecture running the CIFAR-10 dataset, the proposed 2T1FeFET CiM design achieves 89.45% CIFAR-10 test accuracy. Compared to previous FeFET based CiM designs, it exhibits immunity to temperature drift at an 8-bit wordlength scale, and achieves better energy efficiency with 2866 TOPS/W.

关键词： Semiconductor device modeling Power demand Nonvolatile memory Microprocessors Neural networks Computer architecture Energy efficiency

Unleashing the Power of Edge-Cloud Generative AI in Mobile Networks: A Survey of AIGC Services

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arXiv 2023年

作者： Xu, Minrui Du, Hongyang Niyato, Dusit Kang, Jiawen Xiong, Zehui Mao, Shiwen Han, Zhu Jamalipour, Abbas Kim, Dong In Shen, Xuemin Leung, Victor C.M. Poor, H. Vincent The School of Computer Science and Engineering Nanyang Technological University Singapore639798 Singapore The School of Automation Guangdong University of Technology Key Laboratory of Intelligent Information Processing and System Integration of IoT Ministry of Education Guangzhou510006 China Guangdong-HongKong-Macao Joint Laboratory for Smart Discrete Manufacturing Guangzhou510006 China The Pillar of Information Systems Technology and Design Singapore University of Technology and Design Singapore487372 Singapore The Department of Electrical and Computer Engineering Auburn University AuburnAL36849-5201 United States The Department of Electrical and Computer Engineering University of Houston HoustonTX77004 United States The Department of Computer Science and Engineering Kyung Hee University Seoul446-701 Korea Republic of The School of Electrical and Information Engineering University of Sydney SydneyNSW2006 Australia The Department of Electrical and Computer Engineering Sungkyunkwan University Suwon16419 Korea Republic of The Department of Electrical and Computer Engineering University of Waterloo WaterlooONN2L 3G1 Canada The College of Computer Science and Software Engineering Shenzhen University Shenzhen518061 China The Department of Electrical and Computer Engineering The University of British Columbia VancouverBCV6T 1Z4 Canada The Department of Electrical and Computer Engineering Princeton University PrincetonNJ08544 United States

Artificial Intelligence-Generated Content (AIGC) is an automated method for generating, manipulating, and modifying valuable and diverse data using AI algorithms creatively. This survey paper focuses on the deployment of AIGC applications, e.g., ChatGPT and Dall-E, at mobile edge networks, namely mobile AIGC networks, that provide personalized and customized AIGC services in real time while maintaining user privacy. We begin by introducing the background and fundamentals of generative models and the lifecycle of AIGC services at mobile AIGC networks, which includes data collection, training, fine-tuning, inference, and product management. We then discuss the collaborative cloud-edge-mobile infrastructure and technologies required to support AIGC services and enable users to access AIGC at mobile edge networks. Furthermore, we explore AIGC-driven creative applications and use cases for mobile AIGC networks. Additionally, we discuss the implementation, security, and privacy challenges of deploying mobile AIGC networks. Finally, we highlight some future research directions and open issues for the full realization of mobile AIGC networks. © 2023, CC BY.

关键词： Life cycle

Wideband Antenna-in-Package Dielectric Resonator Antenna Using High-Resistance Silicon Substrate for Satellite Communications

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Wideband Antenna-in-Package Dielectric Resonator Antenna Usi...

UK, Europe, China Millimeter Waves and THz Technology Workshop (UCMMT)

作者： Ning-Shuang Fang Qiang Wang Li-Tao Chen Kwok Wa Leung Nan Yang Kai Lu Guodong Su Yunliang Long School of Electronics and Information Technology (School of Microelectronics) and Guangdong Provincial Key Laboratory of Optoelectronic Information Processing Chips and Systems Sun Yat-Sen University Guangzhou China Comba Telecom Technology (Guangzhou) Limited Department of Electronic Engineering State Key Laboratory of Terahertz and Millimeter Waves City University of Hong Kong China Information and Communication Technology Center CityU Shenzhen Research Institute Shenzhen China Zhejiang Provincial Laboratory of Integrated Circuit Design Hangzhou Dianzi University Hangzhou China

A wideband antenna-in-package (AiP) dielectric resonator antenna (DRA) is presented in this paper. Air vias and metallic vias are used to form the equivalent DRA. To obtain a wideband design, a slot-loaded DRA mode and a fundamental DRA mode are simultaneously excited. Two metal strips are attached on the top surface for better impedance matching. To verify the design idea, a prototype is designed with a simulated bandwidth larger than 20 %. It should be mentioned that the presented design is compatible with silicon-based process, and thus suitable for AiP and heterogeneous integration systems.

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