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A 60GHz BiCMOS self-demodulator with injection locked oscillator

A 60GHz BiCMOS self-demodulator with injection locked oscill...

引用

8th International SoC design Conference 2011, ISOCC 2011

作者： Lu, Zhenghao Yu, Xiao Peng Yeo, Kiat Seng Lim, Wei Meng Yan, Jinna Pan, Renjing Department of Microelectronics Soochow University Suzhou 215006 China Institute of VLSI Design Zhejiang University Hangzhou 310027 China Division of Circuits and Systems School of Electrical and Electronic Engineering Nanyang Technological University Singapore 639798 Singapore

ISBN: (纸本)9781457707100

This paper proposes a wide-band self-demodulating receiver for 60GHz ISM band applications. The proposed receiver architecture self-demodulates the OOK input signal by using injection locked oscillator and passive mixer. This simple architecture features extremely ultra-lower-power consumption and faster settling time. Implemented in Tower Jazz 180nm SiGe technology with 200GHz fT, the proposed receiver is able to work at the 60GHz ISM-band frequency range with an OOK data rate up to 2Gbps. The current consumption of the whole receiver is less than 15mA from a single 1.8V supply. ©2011 IEEE.

关键词： Si-Ge alloys

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Hardware reuse in modern application-specific processors and accelerators

Hardware reuse in modern application-specific processors and...

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2011 14th Euromicro Conference on Digital System design: Architectures, Methods and Tools, DSD 2011

作者： Nery, Alexandre S. Jozwiak, Lech Lindwer, Menno Cocco, Mauro Nedjah, Nadia França, Felipe M.G. LAM - Computer Architecture and Microelectronics Laboratory Systems Engineering and Computer Science Program COPPE Universidade Federal do Rio de Janeiro Brazil Department of Electronics Engineering and Telecommunications Faculty of Engineering Universidade do Estado do Rio de Janeiro Brazil Department of Electrical Engineering - Electronic Systems Eindhoven University of Technology Netherlands Silicon Hive - Intel UMG Netherlands

ISBN: (纸本)9780769544946

Effective exploitation of the application-specific parallel patterns and computation operations through their direct implementation in hardware is the base for construction of high-quality application-specific (re-) configurable application specific instruction set processors (ASIPs) and hardware accelerators for modern highly-demanding applications. Although it receives a lot of attention from the researchers and practitioners, a very important problem of hardware reuse in ASIP and accelerator synthesis is clearly underestimated and does not get enough attention in the published research. This paper is an effect of an industry and academic collaborative research. It analyses the problem of hardware sharing, shows its high practical relevance, as well as a big influence of hardware sharing on the major circuit and system parameters, and its importance for the multi-objective optimization and tradeoff exploitation. It also demonstrates that the state-of-the-art synthesis tools do not sufficiently address this problem and gives several guidelines related to enhancement of the hardware reuse. © 2011 IEEE.

关键词： Multiobjective optimization

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Optimization of F2 layer parameters using IRI-Plas model and IONOLAB Total Electron Content

Optimization of F2 layer parameters using IRI-Plas model and...

引用

International Conference on Recent Advances in Space Technologies

作者： Sahin, Oktay Sezen, Umut Arikan, Feza Arikan, Orhan Aktug, Bahadir Department of Avionics and Naval Systems Design Aselsan Inc. Microelectronics Guidance and Electro-Optics Division Akyurt Ankara 06750 Turkey Department of Electrical and Electronics Engineering Hacettepe University Beytepe Ankara 06800 Turkey Department of Electrical and Electronics Engineering Bilkent University Ankara 06800 Turkey General Command of Mapping Cebeci Ankara Turkey

ISBN: (纸本)9781424496143

In this study, the relation of the maximum ionization height (HmF2) and the critical frequency (FoF2) of F2 layer is examined within their parametric range through the International Reference Ionosphere extended towards the plasmasphere (IRI-Plas) model and the IONOLAB-TEC (Total Electron Content) observations. HmF2 and FoF2 are optimized using an iterational loop through Non-Linear Least Squares method by also using a physical relation constraint between these two parameters. Performance evaluation of optimization algorithm is performed separately for the cases running IRI-Plas with optimized parameters and TEC input;only with optimized parameters;only with TEC and finally with no optimized parameter and TEC input. As a conclusion, it is seen that using optimized parameters and TEC together as input produces best IRI-TEC estimates. But also using only optimized parameters (without TEC update) gives estimates with also very low RMS errors and is suitable to use in optimizations. HmF2 and FoF2 estimates are obtained separately for a quiet day, positively corrupted day, negatively corrupted day, a northern latitude and a southern latitude. HmF2 and FoF2 estimation results are compared with ionosonde data where available. This study enables the modification and update of empirical and deterministic IRI Model to include instantaneous variability of the ionosphere. © 2011 IEEE.

关键词： Ionosphere

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A 60GHz BiCMOS self-demodulator with injection locked oscillator

A 60GHz BiCMOS self-demodulator with injection locked oscill...

引用

International SoC design Conference, ISOCC

作者： Zhenghao Lu Xiao Peng Yu Kiat Seng Yeo Wei Meng Lim Jinna Yan Renjing Pan Department of Microelectronics Soochow University Suzhou China Institute of VLSI Design University of Zhejiang Hangzhou China Division of Circuits and Systems School of Electrical and Electronic Engineering Nanyang Technological University Singapore

This paper proposes a wide-band self-demodulating receiver for 60GHz ISM band applications. The proposed receiver architecture self-demodulates the OOK input signal by using injection locked oscillator and passive mixer. This simple architecture features extremely ultra-lower-power consumption and faster settling time. Implemented in Tower Jazz 180nm SiGe technology with 200GHz f T , the proposed receiver is able to work at the 60GHz ISM-band frequency range with an OOK data rate up to 2Gbps. The current consumption of the whole receiver is less than 15mA from a single 1.8V supply.

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Chip-to-wafer (C2W) 3D integration with well-controlled template alignment and wafer-level bonding

Chip-to-wafer (C2W) 3D integration with well-controlled temp...

引用

Electronic Components and Technology Conference (ECTC)

作者： Qianwen Chen Dingyou Zhang Zheyao Wang Litian Liu James Jian-Qiang Lu Department of Electrical Computer and Systems Engineering Rensselaer Polytechnic Institute Troy NY USA Tsinghua National Laboratory for Information Science and Technology (TNList) Institute of Microelectronics Tsinghua University Beijing China

This paper presents on a novel chip-to-wafer (C2W) three-dimensional (3D) integration technology with well-controlled template alignment and wafer-level bonding, enabling precise alignment, few thermal cycles and high throughput of 3D system fabrication. The key processes are investigated and discussed in detail, including chip edge definition, template fabrication, C2W alignment and wafer-level bonding. The C2W 3D integration technology is successfully demonstrated using Cu daisy chains, a patterned thick benzocyclobutene (BCB) layer on the wafer as the alignment template, and wafer-level C2W Cu-Cu bonding. An alignment accuracy less than 2 μm is achieved. The FIB-SEM images reveal that Cu grains cross the original Cu-Cu bonding interface to form strong bonding. The measured I-V characteristics of daisy chains show a linear ohmic behavior, and the specific contact resistance of Cu-Cu bonding structures is on the order of 10 -8 ohm-cm 2 , suggesting good electric contacts.

关键词： Bonding Copper Three dimensional displays Etching Accuracy Resistance

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Optimization of F2 layer parameters using IRI-Plas model and IONOLAB Total Electron Content

Optimization of F2 layer parameters using IRI-Plas model and...

引用

International Conference on Recent Advances in Space Technologies (RAST)

作者： Oktay Sahin Umut Sezen Feza Arikan Orhan Arikan Bahadir Aktug Department of Avionics and Naval Systems Design Microelectronics Guidance and Electro-Optics Division Aselsan Inc. Ankara Turkey Department of Electrical and Electronics Engineering Hacettepe University Ankara Turkey Department of Electrical and Electronics Engineering Bilkent University Ankara Turkey General Command of Mapping Ankara Turkey

In this study, the relation of the maximum ionization height (HmF2) and the critical frequency (FoF2) of F2 layer is examined within their parametric range through the International Reference Ionosphere extended towards the plasmasphere (IRI-Plas) model and the IONOLAB-TEC (Total Electron Content) observations. HmF2 and FoF2 are optimized using an iterational loop through Non-Linear Least Squares method by also using a physical relation constraint between these two parameters. Performance evaluation of optimization algorithm is performed separately for the cases running IRI-Plas with optimized parameters and TEC input; only with optimized parameters; only with TEC and finally with no optimized parameter and TEC input. As a conclusion, it is seen that using optimized parameters and TEC together as input produces best IRI-TEC estimates. But also using only optimized parameters (without TEC update) gives estimates with also very low RMS errors and is suitable to use in optimizations. HmF2 and FoF2 estimates are obtained separately for a quiet day, positively corrupted day, negatively corrupted day, a northern latitude and a southern latitude. HmF2 and FoF2 estimation results are compared with ionosonde data where available. This study enables the modification and update of empirical and deterministic IRI Model to include instantaneous variability of the ionosphere.

关键词： Estimation Optimization Data models Ionosphere Receivers Computational modeling Sun

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IPF: In-Place X-Filling to Mitigate Soft Errors in SRAM-Based FPGAs

IPF: In-Place X-Filling to Mitigate Soft Errors in SRAM-Base...

引用

International Conference on Field Programmable Logic and Applications

作者： Zhe Feng Naifeng Jing GengSheng Chen Yu Hu Lei He Electrical Engineering Department University of California Los Angeles USA School of Microelectronics Shanghai Jiao Tong University China State Key Laboratory of Application Specific Circuits and Systems Fudan University Shanghai China Electrical and Computer Engineering Department University of Alberta Canada

SRAM-based Field Programmable Gate Arrays (FPGAs) are vulnerable to Single Event Upsets (SEUs). We show that a large portion (40%-60% for the circuits in our experiments) of the total used LUT configuration bits are don't care bits, and propose to decide the logic values of don't care bits such that soft errors are reduced. Our approaches are efficient and do not change LUT level placement and routing. Therefore, they are suitable for design closure. For the ten largest combinational MCNC benchmark circuits mapped for 6-LUTs, our approaches obtain 20% chip level Mean Time To Failure (MTTF) improvements, compared to the baseline mapped by Berkeley ABC mapper. They obtain 3× more chip level MTTF improvements and are 128× faster when compared to the existing best in-place IPD algorithm.

关键词： Table lookup Field programmable gate arrays Integrated circuit interconnections Integrated circuit reliability Observability Helium

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A parallel architecture for ray-tracing with an embedded intersection algorithm

A parallel architecture for ray-tracing with an embedded int...

引用

IEEE International Symposium on Circuits and systems (ISCAS)

作者： Alexandre S. Nery Nadia Nedjah Felipe M.G. França Lech Jozwiak LAM-Computer Architecture and Microelectronics Laboratory Systems Engineering and Computer Science Program COPPE Universidade Federal do Rio de Janeiro Brazil Department of Electrical Engineering-Electronic Systems Eindhovan University of Technology Netherlands Department of Electronics Engineering and Telecommunications-Faculty of Engineering Universidade do Estado do Rio de Janeiro (UERJ) Brazil

Real time rendering of three-dimensional scenes in Ray Tracing is a hard problem. However, parallel implementations have been enabling real time performance, as the algorithm can be highly parallelized. Thus, a custom parallel design in hardware is likely to achieve a good performance. In this paper, we further improve the GridRT architecture overall performance by embedding the ray-triangle intersection computation into the precessing elements that form the architecture. Low cost and high rendering performance are the main concerns in this novel design. The results show that the execution time of each intersection computation is reduced by at least 50%, while the area cost is practically unchanged or even reduced when compared to the original GridRT implementation.

关键词： Ray tracing Registers Equations USA Councils Mathematical model Parallel architectures

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Hardware Reuse in Modern Application-Specific Processors and Accelerators

Hardware Reuse in Modern Application-Specific Processors and...

引用

Euromicro Symposium on Digital System design

作者： Alexandre S. Nery Lech Jozwiak Menno Lindwer Mauro Cocco Nadia Nedjah Felipe M.G. Franca LAM-Computer Architecture and Microelectronics Laboratory Systems Engineering and Computer Science Program COPPE Universidade Federal do Rio de Janeiro Brazil Department of Electrical Engineering-Electronic Systems Eindhoven University of Technology Netherlands Silicon Hive-Intel UMG Netherlands Department of Electronics Engineering and Telecommunications-Faculty of Engineering Universidade do Estado do Rio de Janeiro Brazil

Effective exploitation of the application-specific parallel patterns and computation operations through their direct implementation in hardware is the base for construction of high-quality application-specific (re-)configurable application specific instruction set processors (ASIPs) and hardware accelerators for modern highly-demanding applications. Although it receives a lot of attention from the researchers and practitioners, a very important problem of hardware reuse in ASIP and accelerator synthesis is clearly underestimated and does not get enough attention in the published research. This paper is an effect of an industry and academic collaborative research. It analyses the problem of hardware sharing, shows its high practical relevance, as well as a big influence of hardware sharing on the major circuit and system parameters, and its importance for the multi-objective optimization and tradeoff exploitation. It also demonstrates that the state-of-the-art synthesis tools do not sufficiently address this problem and gives several guidelines related to enhancement of the hardware reuse.

关键词： Hardware Resource management Computer architecture Optimization Program processors Adders Delay

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A Parallel Ray Tracing Architecture Suitable for Application-Specific Hardware and GPGPU Implementations

A Parallel Ray Tracing Architecture Suitable for Application...

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Euromicro Symposium on Digital System design

作者： Alexandre S. Nery Nadia Nedjah Felipa M.G. Franca Lech Jozwiak LAM-Computer Architecture and Microelectronics Laboratory Systems Engineering and Computer Science Program COPPE Universidade Federal do Rio de Janeiro Brazil Department of Electrical Engineering-Electronic Systems Eindhoven University of Technology Netherlands Universidade do Estado do Rio de Janeiro Rio de Janeiro RJ BR

The Ray Tracing rendering algorithm can produce high-fidelity images of 3-D scenes, including shadow effects, as well as reflections and transparencies. This is currently done at a processing speed of at most 30 frames per second. Therefore, actual implementations of the algorithm are not yet suitable for interactive real-time rendering, which is required in games and virtual reality based applications. Fortunately, the algorithm allows for massive parallelization of its computations. In this paper, we present a parallel architecture for ray tracing based on a uniform spatial subdivision of the scene and exploiting an embedded computation of ray-triangle intersections. This approach allows for a significant acceleration of intersection computations, as well as, a reduction of the total number of the required intersections checks. Furthermore, it allows for these checks to be performed in parallel and in advance for each ray. In this paper we discuss and analyze an ASIP-based implementation using FPGAs and a GPGPU-based parallel implementation of the proposed architecture. The performance of both implementations are reported and compared.

关键词： Ray tracing Graphics processing unit Instruction sets Computer architecture Registers Image color analysis Hardware

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