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IEEE International Symposium on Circuits and systems (ISCAS)

作者： Alexandre S. Nery Nadia Nedjah Felipe M.G. França Lech Jozwiak LAM-Computer Architecture and Microelectronics Laboratory Systems Engineering and Computer Science Program COPPE Universidade Federal do Rio de Janeiro Brazil Department of Electrical Engineering-Electronic Systems Eindhovan University of Technology Netherlands Department of Electronics Engineering and Telecommunications-Faculty of Engineering Universidade do Estado do Rio de Janeiro (UERJ) Brazil

Real time rendering of three-dimensional scenes in Ray Tracing is a hard problem. However, parallel implementations have been enabling real time performance, as the algorithm can be highly parallelized. Thus, a custom parallel design in hardware is likely to achieve a good performance. In this paper, we further improve the GridRT architecture overall performance by embedding the ray-triangle intersection computation into the precessing elements that form the architecture. Low cost and high rendering performance are the main concerns in this novel design. The results show that the execution time of each intersection computation is reduced by at least 50%, while the area cost is practically unchanged or even reduced when compared to the original GridRT implementation.

关键词： Ray tracing Registers Equations USA Councils Mathematical model Parallel architectures

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Hardware Reuse in Modern Application-Specific Processors and Accelerators

Hardware Reuse in Modern Application-Specific Processors and...

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Euromicro Symposium on Digital System design

作者： Alexandre S. Nery Lech Jozwiak Menno Lindwer Mauro Cocco Nadia Nedjah Felipe M.G. Franca LAM-Computer Architecture and Microelectronics Laboratory Systems Engineering and Computer Science Program COPPE Universidade Federal do Rio de Janeiro Brazil Department of Electrical Engineering-Electronic Systems Eindhoven University of Technology Netherlands Silicon Hive-Intel UMG Netherlands Department of Electronics Engineering and Telecommunications-Faculty of Engineering Universidade do Estado do Rio de Janeiro Brazil

Effective exploitation of the application-specific parallel patterns and computation operations through their direct implementation in hardware is the base for construction of high-quality application-specific (re-)configurable application specific instruction set processors (ASIPs) and hardware accelerators for modern highly-demanding applications. Although it receives a lot of attention from the researchers and practitioners, a very important problem of hardware reuse in ASIP and accelerator synthesis is clearly underestimated and does not get enough attention in the published research. This paper is an effect of an industry and academic collaborative research. It analyses the problem of hardware sharing, shows its high practical relevance, as well as a big influence of hardware sharing on the major circuit and system parameters, and its importance for the multi-objective optimization and tradeoff exploitation. It also demonstrates that the state-of-the-art synthesis tools do not sufficiently address this problem and gives several guidelines related to enhancement of the hardware reuse.

关键词： Hardware Resource management Computer architecture Optimization Program processors Adders Delay

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A Parallel Ray Tracing Architecture Suitable for Application-Specific Hardware and GPGPU Implementations

A Parallel Ray Tracing Architecture Suitable for Application...

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Euromicro Symposium on Digital System design

作者： Alexandre S. Nery Nadia Nedjah Felipa M.G. Franca Lech Jozwiak LAM-Computer Architecture and Microelectronics Laboratory Systems Engineering and Computer Science Program COPPE Universidade Federal do Rio de Janeiro Brazil Department of Electrical Engineering-Electronic Systems Eindhoven University of Technology Netherlands Universidade do Estado do Rio de Janeiro Rio de Janeiro RJ BR

The Ray Tracing rendering algorithm can produce high-fidelity images of 3-D scenes, including shadow effects, as well as reflections and transparencies. This is currently done at a processing speed of at most 30 frames per second. Therefore, actual implementations of the algorithm are not yet suitable for interactive real-time rendering, which is required in games and virtual reality based applications. Fortunately, the algorithm allows for massive parallelization of its computations. In this paper, we present a parallel architecture for ray tracing based on a uniform spatial subdivision of the scene and exploiting an embedded computation of ray-triangle intersections. This approach allows for a significant acceleration of intersection computations, as well as, a reduction of the total number of the required intersections checks. Furthermore, it allows for these checks to be performed in parallel and in advance for each ray. In this paper we discuss and analyze an ASIP-based implementation using FPGAs and a GPGPU-based parallel implementation of the proposed architecture. The performance of both implementations are reported and compared.

关键词： Ray tracing Graphics processing unit Instruction sets Computer architecture Registers Image color analysis Hardware

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Experimental Characterization of the Reliability of 3-Terminal Dual-Damascene Copper Interconnect Trees

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MRS Online Proceedings Library 2011年第1期716卷 8131-8136页

作者： Gan, C. L. Thompson, C. V. Pey, K. L. Choi, W. K. Wei, F. Yu, B. Hau-Riege, S. P. Advanced Materials for Micro- and Nano- Systems Programme Singapore-MIT Alliance Singapore Department of Materials Science and Engineering Massachusetts Institute of Technology Cambridge USA National University of Singapore now with School of Electrical & Electronics Engineering Nanyang Technological University Nanyang Avenue Singapore Department of Electrical & Computer Engineering National University of Singapore Singapore Institute of Microelectronics San Jose USA Intel Corp. Hillsborough OR 97124 now with Lawrence Livermore National Laboratory Livermore USA

Electromigration experiments have been carried out on simple Cu dual-damascene interconnect tree structures consisting of straight via-to-via (or contact-to-contact) lines with an extra via in the middle of the line. As with Al-based interconnects, the reliability of a segment in this tree strongly depends on the stress conditions of the connected segment. Beyond this, there are important differences in the results obtained under similar test conditions for Al-based and Cu-based interconnect trees. These differences are thought to be associated with variations in the architectural schemes of the two metallizations. The absence of a conducting electromigrationresistant overlayer in Cu technology, and the possibility of liner rupture at stressed vias lead to significant differences in tree reliabilities in Cu compared to Al.

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Comparison between Two Implementations of ParFlow for Simulating Femtocell Networks

Comparison between Two Implementations of ParFlow for Simula...

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International Conference on Computer Communications and Networks (ICCCN)

作者： Guillaume de la Roche Jean-Frederic Wagen Guillaume Villemaud Jean-Marie Gorce Jie Zhang Centre of Wireless Network Design University of Bedfordshire Luton UK Mobile Systems Group UAS-WS Fribourg EIA-FR Fribourg Switzerland CITI Laboratory/INRIA ARES project INSA Lyon Villeurbanne France Department of Electrical Engineering University of Sheffield Sheffield UK

In the context of heterogeneous networks, femtocells are very promising. In order to properly simulate their behavior and their impact on the macrocell layer, it is necessary to be able to simulate the radio coverage of femtocells. Hence ParFlow is a possible deterministic model that can be used for such simulation. In this paper two implementations of ParFlow are presented: time domain and frequency domain. The performance are compared and the advantages/drawbacks of each model are investigated.

关键词： Mathematical model Time domain analysis Computational modeling Planning Finite difference methods Antennas and propagation Accuracy

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Very low effective electromagnetic parameters lenses for the unlicensed 60 GHz band

Very low effective electromagnetic parameters lenses for the...

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International Conference on Infrared and Millimeter Waves

作者： M. Navarro-Cía M. Beruete M. Sorolla T. Akalin N. Engheta Millimeter and Terahertz Waves Laboratory Universidad PÙblica de Navarra Pamplona Spain Experimental Solid State Group Imperial College London London UK Department Electrical and Systems Engineering University of Pennsylvania Philadelphia USA Institute of Electronics Microelectronics and Nanotechnology (IEMN) University of Lille 1 France

In this presentation advances on metallic lenses based on extreme electromagnetic parameters will be shown: either epsilon near zero or epsilon and mu near zero simultaneously. The former is generated by an array of continuous waveguides at cutoff, whereas the latter is composed of stacked subwavelength hole arrays that can be understood as discontinuous waveguides operating below cutoff.

关键词： Lenses Metamaterials Arrays Magnetic materials Electromagnetics Optical ring resonators

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Deterministic chaos can act as a decoherence suppressor

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Physical Review B 2011年第21期84卷 214304-214304页

作者： Jing Zhang Yu-xi Liu Wei-Min Zhang Lian-Ao Wu Re-Bing Wu Tzyh-Jong Tarn Department of Automation Tsinghua University Beijing 100084 People's Republic of China Center for Quantum Information Science and Technology Tsinghua National Laboratory for Information Science and Technology Beijing 100084 People's Republic of China Institute of Microelectronics Tsinghua University Beijing 100084 People's Republic of China Department of Physics and Center for Quantum Information Science National Cheng Kung University Tainan 70101 Taiwan Department of Theoretical Physics and History of Science The Basque Country University (EHU/UPV) and IKERBASQUE Basque Foundation for Science E-48011 Bilbao Spain Department of Electrical and Systems Engineering Washington University St. Louis Missouri 63130 USA

We propose a strategy to suppress non-Markovian decoherence of a qubit by coupling the qubit to a deterministic chaotic setup with the broad power distribution in particular in the high-frequency domain. Although it is widely believed that chaos induces decoherence, we find, surprisingly, that the unitary dynamics induced by the chaotic setup can be helpful for the decoherence suppression. Compared with the existing decoherence control methods such as the usual dynamical decoupling, we do not need to impose high-frequency controls, because the high-frequency components in our method are generated by the chaotic setup, and the design of complex optimized control pulses used in the modified dynamical decoupling approaches is also not necessary. Using superconducting quantum circuits as an example, we demonstrate how to realize our general method. We find that various noises in a wide frequency domain, including low-frequency 1/f, high-frequency ohmic, subohmic, and superohmic noises, can be efficiently suppressed by coupling the qubit to a Duffing oscillator acting as the chaotic setup. Significantly, the decoherence time of the qubit is prolonged approximately 100 times in magnitude.

关键词： MARKOV spectrum SUPERCONDUCTORS OPTICS OHM'S law DIRECT currents

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design of probabilistic-based Markov Random Field logic gates in 65nm CMOS technology

Design of probabilistic-based Markov Random Field logic gate...

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2010 International SoC design Conference, ISOCC 2010

作者： Lu, Zhenghao Yu, Xiao Peng Yeo, Kiat Seng Department of Microelectronics Soochow University Suzhou 215006 China Institute of VLSI Design Zhejiang University Hangzhou 310027 China Division of Circuits and Systems School of Electrical and Electronic Engineering Nanyang Technological University Singapore 639798 Singapore

ISBN: (纸本)9781424486335

As the VLSI technology node is getting into the sub-100nm regime, the reliability issues caused by random interferences such as noise, process variations and manufacturing defects are changing the nature of digital computation from deterministic to probabilistic. This paper studies the principle of probabilistic-based Markov Random Field (MRF) design methodology for CMOS static logic gates. The MRF design technique is able to significantly improve the reliability and interference tolerance of the logic circuits. A Differential Cascode Voltage Switch (DCVS) based MRF logic design method is proposed, which presents substantial noise immunity improvement over the normal MRF logic circuits. The proposed method is validated by simulation in 65nm CMOS technology. ©2010 IEEE.

关键词： Logic gates

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Sampling Spiking Neural Network electronic nose on a tiny-chip

Sampling Spiking Neural Network electronic nose on a tiny-ch...

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Midwest Symposium on Circuits and systems (MWSCAS)

作者： Hoda S. Abdel-Aty-Zohdy Jacob N. Allen Microelectronics & Bio-Inspired Systems Design Department of electrical and Computer Engineering Oakland University Rochester MI USA

Chemicals classification using a new Sampling Spiking Neural Network (SSNN) approach is presented in this paper with experimental measurements using the Cyranose 320 sensor array. The network is unique in its minimal yet powerful design which implements on chip learning and parallel monitoring to detect binary odor patterns with high noise environment. The SSNN architecture is further implemented on a 0.5 um CMOS technology tiny-chip designed to work in conjunction with a 256 K external SRAM memory. It handles the routing of spike signal among 32,000 synapses and 255 neurons. At the same time, it tracks and records learning statistics. The chip can be used in parallel with other SSNN co processors for very large systems. Experimental measurements of our SSNN E-Nose classifier, compared to other E-nose systems proved superior in capability, size, and correctness.

关键词： Sampling methods Neural networks Electronic noses Sensor arrays Chemical sensors Semiconductor device measurement CMOS technology Network-on-a-chip Monitoring Working environment noise

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Spiking Neural Network E-Nose classifier chip

Spiking Neural Network E-Nose classifier chip

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IEEE National Conference on Aerospace and Electronics (NAECON)

作者： Hoda S. Abdel-Aty-Zohdy Jacob N. Allen Robert L. Ewing Microelectronics & Bio-Inspired Systems Design Department of Electrical and Computer Engineering Oakland University Rochester MI USA Center of Innovative Radar Consortium OH USA

Hardware E-Nose system classification is a challenging task. This paper presents our system architecture for chemical classifiers, with our recently developed Sampling Spiking Neural Network (SSNN) approach. The SSNN architecture is implemented on a 0.5 um CMOS technology tiny-chip designed to work in conjunction with a 256K external SRAM memory. It handles the routing of spike signals among 32,000 synapses and 255 neurons. At the same time, it tracks and records learning statistics. The chip can be used in parallel with other SSNN co-processors for very large systems. Experimental measurements using the Cyranose 320 sensor array and the SSNN-1 classifier are presented and results compare favorably to other E-Nose classification systems. The SSNN-1 is unique in its minimal yet powerful design with on-chip learning and parallel monitoring to detect binary odor patterns with high noise environment.

关键词： Artificial neural networks Neurons Chemicals Olfactory Biological system modeling Mathematical model

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