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检索条件"机构=Microelectronics Systems Design Laboratory Department of Electrical and Systems Engineering"

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Paradigm of design for biosystem-on-a-chip(BioSoC)

Paradigm of design for biosystem-on-a-chip(BioSoC)

引用

IEEE International Conference on Microelectronic systems Education

作者： R.L. Ewing H.S. Abdel-Aty-Zohdy Information Directorate Air Force Research Laboratory Air Force Institute of Technology Department of Electrical and Computer Engineering Wright Patterson Air Force Base OH USA Microelectronics System Design Laboratory Department of Electrical and Systems Engineering Oakland University Rochester MI USA

The paradigm of design for biosystem-on-a-chip (BioSoC), is that multidisciplinary skills are required. Thus, the educational goals are to develop an understanding of micro/macro collaboration along with the ability to apply and use multidisciplinary skills for the design and performance evaluation of a "biosystem on a chip". The need for the architectural design of the BioSoC addresses the next-generation of intelligent information processing systems.

关键词： Intelligent sensors Collaboration design engineering Biology computing Chemical and biological sensors Biosensors Artificial intelligence microelectronics Circuits Chemical sensors

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Dynamic scheduling issues in SMT architectures

Dynamic scheduling issues in SMT architectures

引用

International Symposium on Parallel and Distributed Processing (IPDPS)

作者： Chulho Shin Seong-Won Lee J.-L. Gaudiot Samsung Electronics Corporation System Design Technology Laboratory Department of Electrical Engineering-Systems University of Southern California USA Department of Electrical Engineering and Computer Science University of California Irvine USA

Simultaneous multithreading (SMT) attempts to attain higher processor utilization by allowing instructions from multiple independent threads to coexist in a processor and compete for shared resources. Previous studies have shown, however, that its throughput may be limited by the number of threads. A reason is that a fixed thread scheduling policy cannot be optimal for the varying mixes of threads it may face in an SMT processor. Our adaptive dynamic thread scheduling (ADTS) was previously proposed to achieve higher utilization by allowing a detector thread to make use of wasted pipeline slots with nominal hardware and software costs. The detector thread adaptively switches between various fetch policies. Our previous study showed that a single fixed thread scheduling policy presents much room (some 30%) for improvement compared to an oracle-scheduled case. In this paper, we take a closer look at ADTS. We implemented the functional model of the ADTS and its software architecture to evaluate various heuristics for determining a better fetch policy for a next scheduling quantum. We report that performance could be improved by as much as 25%.

关键词： Dynamic scheduling Surface-mount technology Yarn Processor scheduling Detectors Multithreading Throughput Face detection Adaptive scheduling Pipelines

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Application specific coarse-grained FPGA for processing element in real time parallel particle filters

Application specific coarse-grained FPGA for processing elem...

引用

IEEE International Workshop on System-on-Chip for Real-Time Applications

作者： M. Sadasivam Sanjing Hong Mobile Systems Design Laboratory Department of Electrical and Computer Engineering State University of New York Stony Brook Stony Brook NY USA

This paper presents an application specific reconfigurable architecture based on coarse-grain FPGA for real-time parallel particle filters. The architecture consists of a set of heterogeneous arithmetic units and buffer banks, where their interconnections are reconfigurable at the hardware level. The proposed architecture separates fixed and reconfigurable units for high-throughput realization. We compare potential throughput of the design with that of commercial FPGAs and DSPs. The proposed architecture is implemented in 0.25 /spl mu/m CMOS process.

关键词： Field programmable gate arrays Particle filters Computer architecture Throughput Digital signal processing Particle tracking Filtering Application software Reconfigurable architectures Real time systems

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Piecewise-linear modeling of analog circuits using trained feed-forward neural networks and adaptive clustering of hidden neurons

Piecewise-linear modeling of analog circuits using trained f...

引用

International Joint Conference on Neural Networks (IJCNN)

作者： S. Doboli G. Gothoskar A. Doboli Computer Science Department Hofstra University Hempstead NY USA VLSI Systems Design Laboratory Electrical and Computer Engineering Department SUNY Stony Brook Stony Brook NY USA

This paper presents a new technique for automatically creating analog circuit models. The method extracts piecewise linear models from trained neural networks. A model is a set of linear dependencies between circuit performances and design parameters. The paper illustrates the technique for an OTA circuit - an amplifier circuit widely used in filters and A/D converters for which models for gain and bandwidth were automatically generated. As experiments show, the obtained models have simple form that accurately fits the sampled points and the behavior of the trained neural networks. These models are useful for fast simulation of systems with non-linear behavior and performances.

关键词： Piecewise linear techniques Analog circuits Feedforward systems Neural networks Feedforward neural networks Adaptive systems Neurons Filters Bandwidth Circuit simulation

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Collaborative QoS architecture between DiffServ and 802.11e wireless LAN

Collaborative QoS architecture between DiffServ and 802.11e ...

引用

IEEE Conference on Vehicular Technology (VTC)

作者： Seyong Park Kyungtae Kim D.C. Kim Sunghyun Choi Sangjin Hong Mobile Systems Design Laboratory Department of Electrical and Computer Engineering State University of New York Stony Brook Stony Brook NY USA Multimedia & Wireless Networking Laboratory School of Electrical Engineering Seoul National University Seoul South Korea

As the multimedia applications such as voice over IP (VoIP) and audio/visual (AV) streaming across the Internet emerge, many are working on the network architecture to extend such applications to the wireless networking domain. The emerging IEEE 802.11e quality-of-service (QoS)-enabled wireless LAN (WLAN) is considered a strong candidate for the air interface for such multimedia applications thanks to the IP-centric network paradigm along with its inherent high-speed transmission capability. This paper provides an integrated wired/wireless network architecture interfacing QoS between user level traffic over IP using differentiated service (Diffserv) and transport level traffic using IEEE 802.11e WLAN. Our study investigates the correlations in end-to-end traffic management between Diffserv and 802.11e, and presents the hierarchical QoS signaling interface between Diffserv and 802.11e, in terms of traffic classifying, shaping and policing.

关键词： Collaboration Diffserv networks Wireless LAN Telecommunication traffic Streaming media Collaborative work Internet telephony IP networks Quality of service Wireless networks

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Analysis of IR-drop scaling with implications for deep submicron P/G network designs

Analysis of IR-drop scaling with implications for deep submi...

引用

IEEE International Symposium on Quality Electronic design

作者： A.H. Ajami K. Banerjee A. Mehrotra M. Pedram Magma Design Automation Cupertino CA USA Department of Electrical Engineering-Systems University of Southern California Los Angeles CA USA Electrical and Computer Engineering Department University of California슠Santa Barbara Santa Barbara CA USA Computer and System Research Laboratory University of Illinois Urbana-Champaign IL USA

This paper presents a detailed analysis of the power-supply voltage (IR) drop scaling in DSM technologies. For the first time, the effects of temperature, electromigration and interconnect technology scaling (including resistivity increase of Cu interconnects due to electron surface scattering and finite barrier thickness) are taken into consideration during this analysis. It is shown that the IR-drop effect in the power/ground (P/G) network increases rapidly with technology scaling, and using well-known counter measures such as wire-sizing and decoupling capacitor insertion with resource allocation schemes that are typically used in the present designs may not be sufficient to limit the voltage fluctuations over the power grid for future technologies. It is also shown that such voltage drops on power lines of switching devices in a clock network can introduce significant amount of skew which in turn degrades the signal integrity.

关键词： Voltage Land surface temperature Electromigration Conductivity Electrons Scattering Counting circuits Power measurement Switched capacitor networks Resource management

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A CAD framework for co-design and analysis of CMOS-SET hybrid integrated circuits 03

A CAD framework for co-design and analysis of CMOS-SET hybri...

引用

IEEE International Conference on Computer-Aided design

作者： S. Mahapatra K. Banerjee F. Pegeon A.M. Ionescu Electronics Laboratory (LEG) Institute of Microelectronics and Microsystems (IMM) Swiss Federal Institute of Technology Lausanne Switzerland Electronics Laboratory (LEG) Swiss Federal Institute of Technology Lausanne (EPFL) Lausanne Switzerland Department of Electrical & Computer Engineering University of California Santa Barbara CA USA Silvaco Data Systems Inc. Grenoble France Silvaco Data Systems Grenoble France

ISBN: (纸本)9781581137620

This paper introduces a CAD framework for co-simulation of hybrid circuits containing CMOS and SET (Single Electron Transistor) devices. An improved analytical model for SET is also formulated and shown to be applicable in both digital and analog domains. Particularly, the extension of the recent MIB model for single/multi gate symmetric/asymmetric device for a wide range of drain to source voltage and temperature is addressed. Circuit level co-simulations are successfully performed by implementing the SET analytical model in Analog Hardware Description Language (AHDL) of a professional circuit simulator SMARTSPICE. Validation at device and circuit level is carried out by Monte-Carlo simulations. Some novel functionality hybrid CMOS-SET circuit characteristics: (i) SET neuron, (ii) Multiple valued logic circuit and (iii) a new Negative Differential Resistance (NDR) circuit, are also predicted by the proposed SET model and analyzed using the new hybrid simulator.

关键词： Hybrid integrated circuits Analytical models Circuit simulation Predictive models Single electron transistors Semiconductor device modeling Voltage Temperature distribution Hardware design languages Neurons

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A hardware implementation of genetic algorithms for measurement characterization

A hardware implementation of genetic algorithms for measurem...

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9th IEEE International Conference on Electronics, Circuits and systems, ICECS 2002

作者： Sharawi, Mohammad S. Quinlan, James Abdel-Aty-Zohdy, Hoda S. Microelectronics System Design Laboratory Electrical and Systems Engineering Oakland University Rochater MI 48309 United States

ISBN: (纸本)0780375963

Integrated circuits that sense, receive, transmit, and process signals are the eye, ears, and nose of the hitechnical field of the millennium. To process/store/analyee signals acquired from sensors, hybrid systems with Rexible and adaptable Intelligent Information Processing and Perception (IIPP) are needed. Genetic Algorithms (GA) present a suitable pre-processing operation hecause of their good convergence to optimum solutions and characterination capabilities. Most of GAs are built via software because of their ease of editing and eustomization. Less attention has been given to hardware implementation of such algorithms. In this paper we present a hardware design approach of a GA for optimum measurements representationjcharacterization to a following IIPP stage. A multilevel verification of the GA is performed via VHDL. In particular the design of efficient universal multipliers and dividers is addressed. A new time efficient approach for Crossover based on preassigned least error value is proposed. The Crossover scheme is called Half Siblings and D Clone. Such a scheme needs 10 iterations to converge the system proposed for sensor measurement characterization. This takes 7680 clock cycles, which is only 96 μsec when implemented in the 0.25 pm CMOS technology. © 2002 IEEE.

关键词： Genetic algorithms

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Analog multiplexing in time domain for biochemical measurement processing

Analog multiplexing in time domain for biochemical measureme...

引用

Midwest Symposium on Circuits and systems (MWSCAS)

作者： A. Patel T. Terry H.S. Abdel-Aty-Zohdy Microelectronics System Design Laboratory (MSDL) Electrical and Systems Engineering Department Oakland University Rochester MI USA

Digital Multiplexers and Analog multiplexers, through the use of filters and their applications implemented in frequency domain, which requires extensive hardware and is costly have seen substantial amount of research compared to an analog multiplexer in time domain. This Paper Presents design, Simulation, Implementation and Evaluation of a four-to-one analog multiplexer. The analog multiplexer is implemented with the help of four buffers and four transmission gates using 0.35 /spl mu/m CMOS Technology with optimum linear ranges that covers 60% of total input supply voltage. The analog multiplexer is developed for a biochemical preprocessing unit to multiplex time-varying analog input signals coming from real-time sensor arrays and to connect the selected input to one A/D converter for digital implementation of a bio-inspired intelligent signal detection system or to an analog implemented biochemical detection system.

关键词： Time measurement Multiplexing Sensor arrays CMOS technology Intelligent sensors Digital filters Frequency domain analysis Hardware Voltage Data preprocessing

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A hardware implementation of genetic algorithms for measurement characterization

A hardware implementation of genetic algorithms for measurem...

引用

IEEE International Conference on Electronics, Circuits and systems (ICECS)

作者： M.S. Sharawi J. Quinlan H.S. Abdel-Aty-Zohdy Microelectronics System Design Laboratory Electrical and Systems Engineering Oakland University Rochester MI USA

To process/store/analyze signals acquired from sensors, hybrid systems with flexible and adaptable intelligent information processing and perception (IIPP) are needed. Genetic algorithms (GA) present a suitable pre-processing operation because of their good convergence to optimum solutions and characterization capabilities. Most GAs are built via software because of their ease of editing and customization. Less attention has been given to hardware implementation of such algorithms. We present a hardware design approach of a GA for optimum measurement representation/characterization to a following IIPP stage. A multilevel verification of the GA is performed via VHDL. In particular the design of efficient universal multipliers and dividers is addressed. A new time efficient approach for crossover based on preassigned least error value is proposed. The crossover scheme is called half siblings and a clone. Such a scheme needs 10 iterations to converge the system proposed for sensor measurement characterization. This takes 7680 clock cycles, which is only 96 /spl mu/sec when implemented in the 0.25 /spl mu/m CMOS technology.

关键词： Hardware Genetic algorithms Intelligent sensors Sensor phenomena and characterization Sensor systems CMOS technology Information analysis Signal analysis Signal processing Information processing

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