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检索条件"机构=Microelectronics Systems Design Laboratory Department of Electrical and Systems Engineering"

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A high-speed multi-port data buffer design for low-energy DSP applications

A high-speed multi-port data buffer design for low-energy DS...

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Annual IEEE International ASIC/SOC Conference

作者： Sangjin Hong Shu-Shin Chin Fanshi Zhao Mobile Systems Design Laboratory Mobile Systems Design Laboratory Department of Electrical and Computer Engineering State University of New York Stony Brook Stony Brook NY USA

ISBN: (纸本)0780367413

Area and power of data storage elements can be excessively large in many data intensive DSP ASICs, such as high-throughput pipelined-FFTs and data interleavers. In this paper, we present a low-complexity multi-port data buffer design methodology based on dynamic memory configuration that results in small area and low power overhead by adapting the buffer architecture to the data access requirements. The buffer minimizes the number of transistors and simplifies-the interface between memory core and external digital circuitry. The buffer can be designed with a low cost digital circuit processing technology. To evaluate our methodology, we designed a buffer for data interleaver and pipelined FFT that requires high throughput. We compare the buffer with conventional buffers based on static memory.

关键词： Computer buffers Digital signal processing Application specific integrated circuits Digital circuits design methodology Digital signal processing chips Random access memory Application software Flexible printed circuits Throughput

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Optimal-weights sensors-measurement fusion using genetic algorithms

Optimal-weights sensors-measurement fusion using genetic alg...

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Midwest Symposium on Circuits and systems (MWSCAS)

作者： M.S. Sharawi H.S. Abdel-Aty-Zohdy R.L. Ewing Microelectronics System Design Laboratory Electrical and Systems Engineering Oakland University Rochester MI USA US Air Force Research Laboratory Dayton OH USA

ISBN: (纸本)078037150X

Although there are many simulated Genetic Algorithms (GAs) in applications, less research has been directed toward their practical hardware implementations. In this paper we present a GA for optimum sensors-measurement fusion and characteristic weights. A multilevel verification of the GA is performed via the Mentor Graphics design Architect (DA) and ModelSim CAD tools. In particular the design of efficient universal multipliers, dividers, and their integrated circuits is addressed. Effective mutation and crossover approach has been implemented in the GA system operation. It requires 960 clock cycles for complete iteration of 64 chromosomes, each with 3 genes of two binary-bits. This requires only 12 /spl mu/sec when implemented in the 0.25 /spl mu/m CMOS technology. The GA system is developed for a preprocessing unit to select optimal weights from real-time sensors measurement, and for fused measurements as in an electronic nose, integrated accelerometer systems, and for performance enhancement of recurrent dynamic neural networks in noisy environments. The proposed approach, simulation results, and possible experimental results are presented.

关键词： Genetic algorithms CMOS technology Hardware Graphics design automation Genetic mutations Clocks Biological cells Integrated circuit technology Real time systems

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design approach for biomedical smart sensors

Design approach for biomedical smart sensors

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Midwest Symposium on Circuits and systems (MWSCAS)

作者： R.L. Ewing H.S. Abdel-Aty-Zohdy Air Force Research Laboratory Inforamation Directorate Adjunct Professor Department of Electrical and Computer Engineering Air Force Institute of Technology USA Microelectronics System Design Laboratory Department of Electrical and Systems Engineering Oakland University Rochester MI USA

ISBN: (纸本)078037150X

System-on-Chip solid state circuits that sense, receive, transmit, and process signals are the sensors, or eyes and ears, of the medical field of the millennium. The goal and design of the System-on-Chip (SOC) program for industry will be to provide affordable, reproducible, and reliable front-end instrumentation, components and subsystems for medical systems. To process/store/analyze the signals acquired from these medical sensors, analog/digital systems are used to provide data fusion and information extraction. These biomedical smart sensors cover the hybrid domains of mixed-technology (electrical, mechanical, optical, thermal, biochemical) and mixed-concept (electrical, control, digital signal processing). These significant domain design differences impose robust design challenges for medical sensor technology.

关键词： Intelligent sensors Biosensors System-on-a-chip Signal processing Sensor systems Mechanical sensors Solid state circuits Eyes Ear Instruments

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A design strategy for a 1-V rail-to-rail input/output CMOS opamp

A design strategy for a 1-V rail-to-rail input/output CMOS o...

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IEEE International Symposium on Circuits and systems (ISCAS)

作者： C.J.B. Fayomi M. Sawan G.W. Roberts Department of Electrical and Computer Engineering Ecole Polytechnique de Montreal Montreal Canada Microelectronics and Computer Systems Laboratory McGill University Montreal Canada

ISBN: (纸本)0780366859

A design strategy for a rail-to-rail input/output operational amplifier in standard CMOS 0.18 /spl mu/m digital process with a 0.5-V threshold is presented. It uses a novel level shifting technique of the input signal and a dynamically biased class AB output stage based on a switched-capacitor configuration. The amplifier is capable of working with a power supply as low as 1-V while providing a 26.6 MHz unity gain frequency and a 67 degree phase margin with a load condition of 5 pF and 20 k/spl Omega/. The overall circuit dissipates 400 /spl mu/W.

关键词： Rail to rail inputs Circuits Voltage Power supplies CMOS process Operational amplifiers Dynamic range Wide area networks microelectronics Laboratories

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A 1-V, 10-bit rail-to-rail successive approximation analog-to-digital converter in standard 0.18 /spl mu/m CMOS technology

A 1-V, 10-bit rail-to-rail successive approximation analog-t...

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IEEE International Symposium on Circuits and systems (ISCAS)

作者： C.J.B. Fayomi G.W. Roberts M. Sawan Department of Electrical and Computer Engineering Ecole Polytechnique de Montreal Montreal Canada Microelectronics and Computer Systems Laboratory McGill University Montreal Canada

ISBN: (纸本)0780366859

Two architectures for a 1-V, 10-bit 200-kS/s successive approximation analog-to-digital converter (ADC) implemented in a standard CMOS 0.18 /spl mu/m digital process are presented. A track-and-hold circuit based on a novel implementation of the bootstrapped low-voltage analog CMOS switch with a novel rail-to-rail track-and-latch comparator circuit is described. A pMOS-only ladder containing a rail-to-rail current-to-voltage converter, performs the DAC function in the second ADC topology whereas a conventional R-2R ladder is used in the first one. Successive approximation and control logic is implemented using of robust single clock phase D flip flop.

关键词： Analog-digital conversion CMOS technology Circuits Power supplies CMOS process Threshold voltage Dynamic range Wide area networks microelectronics Laboratories

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Integrated hardware-software co-synthesis for design of embedded systems under power and latency constraints 01

Integrated hardware-software co-synthesis for design of embe...

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Proceedings of the conference on design, automation and test in Europe

作者： A. Doboli VLSI Systems Design Laboratory Department of Electrical and Computer Engineering State University of New York (SUNY) at Stony Brook Stony Brook NY

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Integrated hardware-software co-synthesis and high-level synthesis for design of embedded systems under power and latency constraints

Integrated hardware-software co-synthesis and high-level syn...

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design, Automation and Test in Europe Conference and Exhibition

作者： A. Doboli VLSI Systems Design Laboratory Department of Electrical and Computer Engineering State University of New York Stony Brook Stony Brook NY USA

ISBN: (纸本)0769509932

This paper presents an integrated approach to hardware software co-synthesis and HLS for design of low-power embedded systems. The main motivation for this work is that fine trade-offs between latency and power can be explored at the system level only with a detailed knowledge of used hardware resources. Integrated method was realized as a simulated annealing based solution-space exploration. Exploration is guided by Performance Models, that exactly capture the relationship between performances i.e. power consumption and latency and design decisions i.e. binding and scheduling. The proposed approach permits nor only a more accurate latency and power estimation but also the exposure of RTL-level design decisions at the system level. As a result, more effective power-latency trade-offs are possible during co-synthesis as compared to traditional task-level methods.

关键词： High level synthesis Embedded system Delay Hardware Power system modeling Energy consumption Very large scale integration Laboratories Embedded software Annealing

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A 1-V, 10-bit rail-to-rail successive approximation analog-to-digital converter in standard 0.18 μm CMOS technology

A 1-V, 10-bit rail-to-rail successive approximation analog-t...

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2001 IEEE International Symposium on Circuits and systems, ISCAS 2001

作者： Fayomi, Christian Jesus B. Roberts, Gordon W. Sawan, Molianiad Ecole Polytechnique de Montreal Department of Electrical and Computer Engineering Station Centre Ville P.0 Box 6079 Montreal H3C 3A7 Canada Microelectronics and Computer Systems Laboratory McGill University Montreal H3A 2A7 Canada

ISBN: (纸本)0780366859

Two architectures for a 1-V, 10-bit 200-kS/s successive approximation analog-to-digital converter (ADC) implemented in a standard CMOS 0.18 μm digital process are presented. A track-and-hold circuit based on a novel implementation of the bootstrapped low-voltage analog CMOS switch with a novel rail-to-rail track-and-latch comparator circuit is described. A pMOS-only ladder containing a rail-to-rail current-to-voltage converter, performs the DAC function in the second ADC topology whereas a conventional R-2R ladder is used in the first one. Successive approximation and control logic is implemented using of robust single clock phase D flip flop. © 2001 IEEE.

关键词： Ladders

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Domain distributed intelligent processing for information fuselets

Domain distributed intelligent processing for information fu...

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IEEE International Symposium on Circuits and systems (ISCAS)

作者： R.L. Ewing H.S. Abdel-Aty-Zohdy US Air Force Research Laboratory Information Directorate Air Force Institute of Technology Dayton OH USA Dept of Electrical & Systems Engineering Microelectronics System Design Laboratory Oakland University Rochester MI USA

ISBN: (纸本)0780366859

The best solution for one intelligent information fusion design is obviously domain specific and not universal. This is especially true in multidisciplinary design domains of information systems at higher clock speeds where the need arises to distribute the intelligent processing requirements between the digital circuit elements and their real world interconnects in the mixed-signal sensor domain. In this paper we propose the distribution of intelligent processing, or fuselets by three levels of information fusion. These are; perception, fuselets, processing algorithms and neural nets. The proposed robust design methodology for multidisciplinary levels, involves the blending of the s-domain (continuous) and z-domain (digital), resulting in the wp-domain (mixed-signal) models. The advantage of using the wp-domain bilinear transformation for mixed-signal design is the ability to handle the discrete portion of the design like a continuous system, thus unifying the design process for domain distributed intelligent processing systems.

关键词： Intelligent sensors Information systems Clocks Digital circuits Integrated circuit interconnections Sensor systems Neural networks Robustness design methodology Continuous time systems

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Transforming the engineering curriculum: Lessons learned from a summer at boeing

Transforming the engineering curriculum: Lessons learned fro...

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作者： Gorman, Michael E. Johnson, Vicki S. Ben-Arieh, David Bhattacharyya, Shankar Eberhart, Scott Glower, Jacob Hoffmann, Klaus Kanda, Arun Kuh, Anthony Lim, Tae Wook Lyrintzis, Anastasios Mavris, Dimitri Schmeckpeper, Edwin Varghese, Philip Wang, Yu University of Virginia United States Embry-Riddle Aero. University United States Kansas State University United States Texas A and M University United States University of Washington United States North Dakota State University United States Wichita State University United States Indian Institute of Technology India University of Hawaii United States University of Kansas United States Purdue University United States Georgia Tech. United States University of Idaho United States University of Texas Austin United States University of Maryland United States Dept. of Industrial Engineering 216 Durland Hall Kansas State University Manhattan KS 66504 United States EE Department Texas A and M University College Station TX 77845 United States Dept. of Aeronautics BOX 352400 University of Washington Seattle WA 98195-2400 United States Dept. of Electrical Engineering North Dakota State University Fargo ND 58105 United States TCC and Systems Engineering Sch. of Engineering Applied Science University of Virginia Charlottesville VA 22902 United States Department of Aerospace Engineering Wichita State University Wichita KS 67260-004 United States Indian Institute of Technology Delhi India Dept. of Electrical Engineering University of Hawaii Honolulu HI 96822 United States Naval Research Laboratory 4555 Overlook Ave. Washington DC 20375 United States Sch. of Aeronautics and Astronautics Grissom Hall Purdue University West Lafayette IN 47907 United States Aerospace Systems Design Laboratory School of Aerospace Engineering Georgia Institute of Technology Atlanta GA 30332-0150 United States Department of Civil Engineering University of Idaho P.O. Box 441022 Moscow ID 83844-1022 United States Center for Aeromechanics Research Department of Aerospace Engineering University of Texas Austin TX 78712-1085 United States Director of Mfg. Automat. Laboratory Department of Mechanical Engineering University of Maryland College Park MD 20742 United States

The Boeing Corporation conducts an A.D. Welliver summer fellowship program for engineering educators. This article describes the lessons learned by the 1998 summer Fellows. These include increasing emphasis on cost, communications and continuous learning, modifying faculty promotion guidelines to honor collaboration in teaching and research, and collaborating with industry on exit criteria. Eventually, industry has to become a partner in the educational process. The Fellows unanimously agreed that the Welliver Program was a valuable experience.

关键词： engineering education

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