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The Pesona16™ RISC 16-bit microprocessor - Architecture, functional configurations, and performances

The Pesona16™ RISC 16-bit microprocessor - Architecture, fu...

引用

2000 4th IEEE International Conference on Semiconductor Electronics, ICSE 2000

作者： Rahman, Airul Azha Abd Rashid, Zainol Abidin Abdul Othman, Masuri Microelectronics Laboratory MIMOS Berhad Malaysia Department of Electrical Electronic and Systems Engineering Universiti Kebangsaan Malaysia Malaysia

The first Malaysian made 16-bit RISC processor the Pesona 16-™ designed and developed by MIMOS is described in terms of its architecture, programming model and its functional capabilities. Performance analysis and com... 详细信息

ISBN: (纸本)0780364309

关键词： Functional programming

来源：评论

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An asynchronous FIFO with fights: case study in speed optimization

An asynchronous FIFO with fights: case study in speed optimi...

引用

IEEE International Conference on Electronics, Circuits and systems (ICECS)

作者： S. Laberge R. Negulescu Microelectronics and Computer Systems Laboratory Department of Electrical and Computer Engineering McGill University Montreal QUE Canada

ISBN: (纸本)0780365429

This paper describes an experiment in optimizing digital integrated circuits to maximize operating speeds. The circuit in question is an asynchronous FIFO originally designed for ultra-high-speed. To obtain an even higher throughput, we consider optimizations and local changes of the circuits by using fights, relative delay constraints, and asymmetric and skewed gates. We propose a transistor sizing procedure applicable in these conditions. Part of our procedure is based on the principles of logical effort; in addition, we investigate how to size the circuit with fights. The resulting circuit implemented in TSMC's 0.35 /spl mu/m technology can yield throughputs over 1500 millions items per second.

关键词： Computer aided software engineering Delay Throughput Logic circuits Capacitance Equations microelectronics Laboratories Digital integrated circuits Constraint optimization

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A robust deep submicron programmable DC voltage generator

A robust deep submicron programmable DC voltage generator

引用

IEEE International Symposium on Circuits and systems (ISCAS)

作者： M.M. Hafed S. Laberge G.W. Roberts Microelectronics and Computer Systems Laboratory Department of Electrical and Computer Engineering McGill University Montreal QUE Canada

An efficient technique for generating accurate on-chip DC reference voltages is presented. The technique is based on filtering a digital pulse-modulated sequence in order to extract its average (DC) value. Simplicity is achieved by using a passive on-chip filter and by using an all-digital implementation of the modulator. Moreover, in addition to using pulse-width modulation to encode the value of the output DC level, we propose the use of pulse-density modulation as a more viable technique. The latter has the advantage of using a significantly smaller filter, which translates into a smaller implementation area and a faster settling time. The technique was successfully demonstrated using a prototype IC in a 0.35 /spl mu/m CMOS process.

关键词： Robustness Voltage DC generators Pulse modulation Digital filters Filtering Passive filters Space vector pulse width modulation Prototypes CMOS integrated circuits

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A stand-alone integrated excitation/extraction system for analog BIST applications

A stand-alone integrated excitation/extraction system for an...

引用

Custom Integrated Circuits Conference (CICC)

作者： M.M. Hafed G.W. Roberts Microelectronics and Computer Systems Laboratory Department of Electrical and Computer Engineering McGill University Montreal QUE Canada

An integrated test core for mixed-signal circuits is described. The core consists of a completely digital implementation, except for a simple reconstruction filter and a comparator. It is capable of both generating arbitrary band-limited waveforms (for excitation purposes) and coherently digitizing arbitrary periodic analog waveforms (for DSP-based test and measurement). A prototype IC was fabricated in a 0.35 /spl mu/m CMOS process and was demonstrated to perform various curve tracing, oscilloscope, and spectrum analysis tasks.

关键词： Built-in self-test Circuit testing Signal generators Application software Hardware Band pass filters microelectronics Laboratories System testing Digital filters

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The Pesona16/sup TM/ RISC 16-bit microprocessor-architecture, functional configurations, and performances

The Pesona16/sup TM/ RISC 16-bit microprocessor-architecture...

引用

IEEE International Conference on Semiconductor Electronics (ICSE)

作者： A.A.A. Rahman Z.A.A. Rashid M. Othman Microelectronics Laboratory MIMOS Berhad Malaysia Department of Electrical Electronic & Systems Engineering Universiti Kebangsaan Malaysia Malaysia

The first Malaysian made 16-bit RISC processor, the Pesona16/sup TM/, designed and developed by MIMOS is described in terms of its architecture, programming model and its functional capabilities. Performance analysis ... 详细信息

ISBN: (纸本)0780364309

关键词： Reduced instruction set computing Microprocessors Registers microelectronics MIMO Functional programming Computer architecture Clocks Decoding Laboratories

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Intelligent information processing using neural networks and genetic algorithms

Intelligent information processing using neural networks and...

引用

Midwest Symposium on Circuits and systems (MWSCAS)

作者： H.S. Abdel-Aty-Zohdy R.L. Ewing Microelectronics System Design Laboratory Electrical and Systems Engineering Oakland University Rochester MI USA U.S. Air Force Research Laboratory Dayton OH USA

Intelligent information processing (IIP) or the smart processing of signals in communication systems and data measurements from multi-sensor systems are needed for advanced microautonomous applications. A balanced combination of efficient algorithms, fast networks, and collaboration of the different technologies are required for smaller, faster, and more efficient system-on-a-chip applications. In this paper we present guidelines/approach for intelligent information processing using neural networks (NNs) and genetic algorithms (GAs) which are capable of learning through discovery and/or reinforcement with features optimization through chromosome mutations of GAs. Specific details about a special application for electronic-nose (EN) implementation to discriminate among four chemicals, using reinforcement NN implemented tiny-chip and a GA system implementation is presented with test results.

关键词： Intelligent networks Information processing Neural networks Signal processing Collaboration System-on-a-chip Guidelines Genetic algorithms Biological cells Genetic mutations

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Full-chip, three-dimensional, shapes-based RLC extraction

Full-chip, three-dimensional, shapes-based RLC extraction

引用

IEEE International Conference on Computer-Aided design

作者： K.L. Shepard D. Sitaram Yu Zheng Columbia Integrated Systems Laboratory Department of Electrical Engineering Columbia University New York NY USA Cadence Design Systems Inc. New Providence NJ USA

In this paper, we report the development of the first commercial full-chip, three-dimensional, shapes-based, RLCK extraction tool, developed as part of a university-industry collaboration. The technique of return-limited inductances is used to provide a sparse, frequency-independent inductance and resistance network with self-inductances that represent sensible "nominal" values in the absence of mutual coupling. Mutual inductances are extracted for accurate noise analysis. The tool, Assura RLCX, exploits high-capacity scan-band techniques and disk caching for inductance extraction as an extension to Cadence's existing Assura RCX extractor.

关键词： Inductance Delay Equations Immune system Timing Propagation losses Wire Frequency Integrated circuit interconnections Circuit noise

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Cell characterization for noise stability

Cell characterization for noise stability

引用

Custom Integrated Circuits Conference (CICC)

作者： K.L. Shepard K. Chou Columbia Integrated Systems Laboratory Department of Electrical Engineering Columbia University New York NY USA CadMOS Design Technology San Jose CA USA

Verifying whether a digital standard-cell design is functional in the presence of interconnect coupling noise is an important concern to ASIC designers. Determining whether the coupling noise occurring on a node is excessive requires comparing this noise against the dynamic noise margins of the receiving gates. The noise stability requirement, introduced in the context of transistor-level static noise analysis, is a technique for quantifying these AC noise margins. In this paper, we describe a technique for modelling noise stability in the form of a four-parameter rule which can be used to characterize the cells of a digital standard-cell library.

关键词： Circuit noise Integrated circuit interconnections Circuit stability Integrated circuit noise Pulse circuits Stability analysis Logic gates Time domain analysis Inverters Laboratories

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A maintainability model for industrial software systems using design level metrics

A maintainability model for industrial software systems usin...

引用

Working Conference on Reverse engineering

作者： S. Muthanna K. Kontogiannis K. Ponnambalam B. Stacey Department of Electrical & Computer Engineering University of Waterloo Waterloo ONT Canada Nortel SEAL Laboratory University of Waterloo Ottawa Canada Department of Systems Design Engineering University of Waterloo Waterloo ONT Canada

ISBN: (纸本)0769508812

Software maintenance is a time consuming and expensive phase of a software product's life-cycle. The paper investigates the use of software design metrics to statistically estimate the maintainability of large software systems, and to identify error prone modules. A methodology for assessing, evaluating and, selecting software metrics for predicting software maintainability is presented. In addition, a linear prediction model based on a minimal set of design level software metrics is proposed. The model is evaluated by applying it to industrial software systems.

关键词： Computer industry Software systems Software design Software maintenance Software metrics Software quality Maintenance engineering design engineering Seals Predictive models

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Low power/low voltage high speed CMOS differential track and latch comparator with rail-to-rail input

Low power/low voltage high speed CMOS differential track and...

引用

IEEE International Symposium on Circuits and systems (ISCAS)

作者： C.J.B. Fayomi G.W. Roberts M. Sawan Dept. of Electr. & Comput. Eng. Ecole Polytech. Montreal Que. Canada Microelectronics and Computer Systems Laboratory McGill University Montreal Canada Department of Electrical and Computer Engineering Ecole Polytechnique de Montreal Montreal Canada

A new CMOS differential latched comparator suitable for low voltage, low-power application is presented. The circuit consists of constant-gm rail-to-rail common-mode operational transconductance amplifier followed by a regenerative latch in a track and latch configuration to achieve a relatively constant delay. The use of a track and latch minimizes the total number of gain stages required for a given resolution. Potential offset from the constant-g/sub m/ differential input stage, estimated as the main source of offset, can be minimized by proper choice of transistors sizes. Simulation results show that the circuit requires less than 86 /spl mu/A with a supply voltage of 1.65 V in a standard CMOS 0.18 /spl mu/m digital process. The average delay is less than 1 ns and is approximately independent of the common-mode input voltage.

关键词： Low voltage Latches Delay Rail to rail operation Transconductance Operational amplifiers Rail to rail amplifiers Circuit simulation CMOS digital integrated circuits CMOS process

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