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Transparent random access memory testing for pattern sensitive faults

JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS 1996年第3期9卷 251-266页

作者： Karpovsky, MG Yarmolik, VN Research Laboratory of Design and Testing of Computer Hardware Department of Electrical Computer and Systems Engineering Boston University Boston USA

This paper presents a new methodology for RAM testing based on the PS(n, k) fault model (the k out of n pattern sensitive fault model). According to this model the contents of any memory cell which belongs to an n-bit memory block, or the ability to change the contents, is influenced by the contents of any k-1 cells from this block. The proposed methodology is a transparent BIST technique, which can be efficiently combined with on-line error detection. This approach preserves the initial contents of the memory after the rest and provides for a high fault coverage for traditional fault and error models, as well as for pattern sensitive faults. This paper includes the investigation of testing approaches based on transparent pseudoexhaustive testing and its approximations by deterministic and pseudorandom circular tests. The proposed methodology can be used for periodic and manufacturing testing and require lower hardware and time overheads than the standard approaches.

关键词： random access memory memory testing exhaustive memory testing transparent memory testing built-in self-test pseudo-exhaustive memory testing pattern sensitive faults signature analysis

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An improved ASIC design and implementation for color space conversion applications

An improved ASIC design and implementation for color space c...

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Midwest Symposium on Circuits and systems (MWSCAS)

作者： M. Nsour H.S. Abdel-Aty-Zohdy Microelectronics System Design Laboratory Department of Electrical and Systems Engineering Oakland University Rochester MI USA

The design and VLSI implementation of an ASIC chip, which performs real time conversion, the Red, Green, and Blue (RGB) color coordinates to CIE (Commission Internationale de l'Eclairage) standard L* (luminance), a* (redness-greenness), and b* (yellowness-blueness) color coordinates, is presented. High-speed operation of this ASIC is achieved by pipelining the input data, and performing parallel operations. The ASIC is implemented using CMOS, 2.0 /spl mu/m, n-well process. It occupies an area of 1.55/spl times/1.45 mm/sup 2/. The chip is intended to be used in colorimetry manufacturing inspection and robotics precision. Inputs are 3 bits each. a* and b* are 7 bits each, L* is 6 bits.

关键词： Application specific integrated circuits systems engineering and theory Inspection Application software Humans Extraterrestrial measurements Instruments Color microelectronics Laboratories

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Uncertain nonlinear algebraic solutions and their implementation using neural networks

Uncertain nonlinear algebraic solutions and their implementa...

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Midwest Symposium on Circuits and systems (MWSCAS)

作者： H.S. Abdel-Aty-Zohdy M.A. Zohdy M. Karam Microelectronics System Design Lab Department of Electrical and Systems Engineering Oakland University Rochester MI USA Department of Electrical and Systems Engineering Oakland University Rochester MI USA

In this article, we propose a dynamic recurrent approach to solve uncertain nonlinear algebraic equations. The approach is justified on the basis of net construction that recursively produces minimum neuron state energy which corresponds to the desired solution. Linearization via the Newton-Raphson method is employed in order to make the net converge to an appropriate region in the solution space. Some preliminary experimentation on non-trivial nonlinear examples are included and discussed. Approaches for hardware implementation of the recurrent dynamic neural network are presented. Comparison between a totally digital chip design and a hybrid analog/digital implementation utilizing MOSIS facilities is made. Evaluation and simulations on system, logic, and circuit levels are emphasized.

关键词： Nonlinear equations Neurons Newton method Neural network hardware Nonlinear dynamical systems Neural networks Recurrent neural networks Chip scale packaging Circuit simulation Logic circuits

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Implementation of time-multiplexed CNN building block cell

Implementation of time-multiplexed CNN building block cell

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International Conference on microelectronics for Neural Networks

作者： K.K. Lai P.H.W. Leong Systems Engineering Design Automation Laboratory Department of Electrical Engineering University of Sydney NSW Australia

We have proposed an area efficient implementation of Cellular Neural Network by using the time-multiplexed method. This paper describes the underlying theory, method, and the circuit architecture of a VLSI implementation. Spice simulation results have been obtained to illustrate the circuit operation. A building block cell of a time-multiplexed cellular neural network has been completed and is currently being fabricated.

关键词： Cellular neural networks Equations Image edge detection Circuits Very large scale integration Mathematical model design engineering systems engineering and theory design automation Laboratories

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PANNE: a parallel computing engine for connectionist simulation

PANNE: a parallel computing engine for connectionist simulat...

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International Conference on microelectronics for Neural Networks

作者： I.Z. Milosavlevich B.G. Flower M.A. Jabri Systems Engineering and Design Automation Laboratory Department of Electrical Engineering University of Sydney Sydney NSW Australia

PANNE (Parallel Artificial Neural Network Engine) is a parallel computing engine aimed at delivering super-computing power to numerical applications such as connectionist simulation and signal processing. The PANNE system exploits the features of the TMS320C40 DSP chip which make it suitable for building parallel computing systems. PANNE has been built with flexibility in mind; it is expandable in terms of hardware resources and supports both shared and distributed memory programming paradigms. We estimate that a system of 16 DSPs would be capable of delivering up to 80/spl times/10/sup 6/ connection updates per second.

关键词： Parallel processing Engines Digital signal processing chips Computational modeling Signal processing algorithms Computer architecture Signal processing Digital signal processing Acceleration Workstations

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Time dependent oxide SiO/sub 2/ breakdown in MOSFET: a consequence of quantum mechanical tunneling of electrons

Time dependent oxide SiO/sub 2/ breakdown in MOSFET: a conse...

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IEEE International Conference on Semiconductor Electronics (ICSE)

作者： M.F. Karim S. Shaari B.Y. Majlis Microelectronics Laboratory Department of Electrical Electronics and Systems Engineering University Kebangsaan Malaysia Bangi Selangor Darul Ehsan Malaysia

Considering the quantum mechanical tunneling of electrons as a leakage current through the thin oxide of a MOSFET, a mathematical model of time dependent dielectric (SiO/sub 2/) breakdown (TDDB) process under high field and current conditions, is developed here. The proposed model involves hole generation, trapping and most importantly high electric field. Impact ionization, occurring by electron tunneling under high field, has been considered as a cause of hole generation. It is believed that the accumulation of positive charges, due to impact ionization within the oxide, results in a decrease in the oxide potential barrier. This provides easy access of excited electrons to the oxide, and thus accelerates the positive charge buildup process. This charge buildup process is time dependent and consequently breaks the oxide potential barrier. In this model, the required time is shown as indicative of the successful operational life time of oxide in digital circuits.

关键词： Tunneling Impact ionization Quantum mechanics Leakage current MOSFET circuits Mathematical model Dielectric breakdown Electron traps Charge carrier processes Acceleration

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Self-organizing feature maps with perfect organization

Self-organizing feature maps with perfect organization

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International Conference on Acoustics, Speech, and Signal Processing (ICASSP)

作者： L. Owsley L. Atlas G. Bernard Interactive Systems Design Laboratory Department of Electrical Engineering University of Washington Seattle WA USA Interactive Systems Design LaboratoryDepartment of Electrical Engineering University of Washington Seattle WA USA Boeing Commercial Airplane Group Seattle WA USA

The self-organizing feature maps (SOFMs) introduced by Kohonen (1990) have found use in a wide variety of signal processing applications. The goal of SOFMs is to allow encoding of high-dimensional data vectors in such a manner that a vector's relative position in the codebook is related to the information in the vector in as simple a fashion as possible. One measure of the SOFM's performance in achieving this goal has been proposed by Zrehen and Blayo (1992). According to this measure, many feature maps produced by previous algorithms were disorganized. We review the Zrehen disorganization measure and some of its characteristics. We then show how our version of the SOFM algorithms can accept some simple modifications to produce feature maps which achieve perfect organization under the Zrehen measure of feature map performance. We discuss the emergent geometric properties of resulting feature maps, and illustrate the results using industrial drill vibration data. We note that applying the Zrehen-constrained algorithm to a data set implies certain assumptions about the set's distribution. We discuss the implications of these assumptions in the context of a feature extraction system for industrial milling data.

关键词： Signal processing algorithms Distortion measurement Frequency measurement Measurement standards Standards organizations Interactive systems Laboratories Airplanes Signal processing Encoding

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The Flexible Hypercube: A New Topology Suitable for Use in Metropolitan Area Networks

The Flexible Hypercube: A New Topology Suitable for Use in M...

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IEEE Workshop on Local and Metropolitan Area Networks (LANMAN)

作者： T. Hameenanttila Xin-Li Guan J.D. Carothers Jian-Xin Chen The University of Arizona Computer Systems Design Laboratory Department of Electrical and Computer Engineering University of Arizona Tucson Tucson AZ USA

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Combinational logic approach for designing RNS multipliers

Combinational logic approach for designing RNS multipliers

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Midwest Symposium on Circuits and systems (MWSCAS)

作者： A.A. Hiasat H. Abdel-Aty-Zohdy Electronics Engineering Department Royal Scientific Society Princess Sumaya University for Technology Amman Jordan Microelectronics System Desigh Laboratory Electrical and Systems Engineering Oakland University Rochester MI USA

The design of Residue Number System (RNS) multipliers has received considerable attention in the last few years. This paper presents a new approach for designing modular multipliers using a combinational logic technique. The idea is based on constructing a truth table whose inputs are the bits of the multiplicand and the multiplier. The outputs are the bits of the modular product. Realizing any minimized Boolean function is achieved using two levels of gates. Compared to most recent developed approach, our new technique requires less integrated circuit area and operates at a higher speed.

关键词： Minimization methods Zinc

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Affordability, logistics R&D and fleet systems

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NAVAL ENGINEERS JOURNAL 1996年第3期108卷 199-213页

作者： Schulte, DP Skolnick, A He has supported the development and operation of several naval systems including advanced component selection for Trident II fire control and navigation systems. He served as branch manager of the Surface Ship ASW Combat System Branch which acted as the acquisition engineering agent for the AN/SQQ-89 Surface Ship Anti-Submarine Warfare Weapon System. He was then selected to manage the Module Engineering Department which provided engineering support to numerous naval systems including the AN/BSY-1 Submarine Combat System and the Trident II fire control and navigation system. He then served as the deputy program manager for NAVSEA Progressive Maintenance (2M/ATE). He holds a B.S. degree in Electrical Engineering from Purdue University and currently is pursuing a Maste's degree in Public Environmental Affairs at Indiana University—Purdue University Indianapolis. He served at Applied Physics Laboratory/The Johns Hopkins University in missile development then aboard USS Boston (CAG-1) and played leading roles in several weapon system developments (Regulus Terrier Tartar Talos) inertial navigation (Polaris) deep submergence (DSRV) and advanced ship designs (SES). He later was director Combat System Integration Naval Sea Systems Command and head Combat Projects Naval Ship Engineering Center. He led the Navy's High Energy Lasers and Directed Energy Weapons development efforts. He was vice president advanced technology at Operations Research Inc. and vice president maritime engineering at Defense Group Inc. before starting SSC in 1991. Dr. Skolnick holds a B.S. degree in Mathematics and Economics Queens College an M.A. degree in Mathematics and Philosophy Columbia University an M.S. degree in Electrical/Aeronautical Engineering U.S. Naval Postgraduate School and a Ph.D. in Electrical Engineering and Applied Mathematics from Polytechnic University in New York. He is the author of many published papers on engineering design issues source selection procedures and large-scale complex technology problems

The Fleet continues to require high performance systems that can operate with dependability in the seas' unforgiving environments and under hostile action. Those demands are not new. What has changed is the urgent priority formerly assigned to national defense issues. The arguments for continued superpower military strength are now roiled in politics along with unsettled budgets and uncertain force level projections. Current expectations revolve about indefinite fiscal and operational issues (difficult funding constraints and broadband threats). In the actual event of ''doing more with less,'' a practical response is to apply the creative power available from sound engineering judgement and the crucible of experience to the immediate needs of the Fleet. The attempt to shorten the path between advanced development effort and Fleet use has been tried occasionally in the past, often, without exemplary results. The Sustainable Hardware and Affordable Readiness Practices (SHARP) program, is a generic R&D effort under OpNav sponsorship that has been working steadily on sensible solutions to product engineering problems. Armed today with fast-time, large-scale computation abilities and modern tools for technical problem solving coupled with specialized engineering knowledge, it has been refreshed and is underway satisfying existing Fleet needs. The relationship between fully responsive engineering services and current operational needs is always demanding. The connection between advanced engineering development (6.3 category funds) and immediate Fleet usage brings added complexity and challenge, both technical and organizational. Illustrative examples of affordable engineering solutions to ''retain, revise, replace or retire'' questions are presented within the context of both Fleet realities and budgetary limitations. The discussion covers legacy system support, civil/military considerations and Fleet maintenance issues. It describes the substantial and critical payoffs i

关键词： Warships

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