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作者： Hossein Sheikhassadi Nasser Masoumi Department of Electrical and Computer Engineering Kerman University Kerman Iran Department Electronics School of ECE College of Engineering University of Tehran Tehran Iran

In current researches, various equivalent circuit models have been demonstrated to study the performance of multiwall carbon nanotubes (MWCNTs). However, most of these models are very complex and predominately use SPICE/HSPICE simulations resulting in high computational time. This paper presents a compact RC model for MWCNT interconnects by different analysis of resistance in RC model. Using this approach, an efficient RC model for MWCNT bundle is also proposed here, for the first time. In this work, delay modeling of MWCNT interconnects is performed by using Elmore delay expression (EDE), that has shown good agreement with the reference model. The percentage error of the delay for both MWCNT and MWCNT bundle interconnects is found to be less than 2%.

关键词： Integrated circuit interconnections Integrated circuit modeling Delay Analytical models Computational modeling Carbon nanotubes Capacitance

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Trimming lithography part I: The alternative technology for sub-resolution and sub-wavelength patterning

Trimming lithography part I: The alternative technology for ...

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International Conference on Electrical engineering/electronics, computer, Telecommunications and Information Technology, ECTI-CON

作者： Nithi Atthi Arreerat Sriklat Wutthinan Jeamsaksiri Charndet Hruanun Amporn Poyai Rardchawadee Silapunt Thai Microelectronics Center (TMEC) National Electronics and Computer Technology Center Thailand Thai Microelectronics Center (TMEC) National Electronics and Computer Technology Center (NECTEC) Department of Electronics and Telecommunication Engineering King Mongkut's University of Technology Thonburi Department of Electronics and Telecommunication Engineering King Mongkut's University of Technology Thonburi Thailand

Lithography is the key technology to scale down a size of integrated circuits that will increase the performance of an electronics device (smaller, faster, cheaper, and low power consumption). There are many lithographic techniques which can produce a nanometer feature size. However, the cost for equipment and mask for those techniques is extremely high. Based on this limitation, this paper introduces an alternative patterning technique called Trimming lithography to produce sub-resolution and sub-wavelength features. The results show that as small as 0.18 μm photoresist linewidth can be produced using the 0.8 μm pattern on a conventional binary mask. The trimming lithography can thus be one of the candidates for future lithography.

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The Effect Injection Width and Temperature-Offset Compensation of Magnetotransistor

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Procedia engineering 2011年 25卷 1269-1272页

作者： Chana Leepattarapongpan Toempong Phetchakul Naritchaphan Penpondee Puttapon Pengpad Arckom Srihapat Wutthinan Jeamsaksiri Charndet Hruanun Amporn Poyai Thai Microelectronics Center (TMEC) National Electronics and Computer Technology Center Chachoengsao Thailand Department of Electronics Faculty of Engineering King Mongkut's Institute of Technology Ladkrabang Bangkok Thailand

This paper presents effect of injection witdh on Magnetotransistor. Emitter area was confined by LOCOS and the injection window size was varied from 4, 5 to 10 microns. With bias current of 3 mA the window size 4 micron gives best sensitivity at 10 mV/T. Measument linearity is 0.1% full scale. voltage gain of 10 was used for minimizing temperature coefficient to be around 7.9 mV/°C measured from 25 to 125 °C. Temperature coefficient divided by sensitivity give us a relative temperature sensitivity of 7.9% T/°C. Second magnetic sensor device has been used for temperature compensation. The second device was config as magnetic field immune then it was used as a temperature offset voltage reference. The added module reduces overall temperature sensitivy down to 0.3% T/°C.

关键词： Magnetotransistor Injection width Hall Effect Temperature-offset compensation

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Physics-based modeling of hole mobility in ultrathin-body silicon-on-insulator MOSFETs

Physics-based modeling of hole mobility in ultrathin-body si...

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作者： Poljak, M. Jovanović, V. Suligoj, T. Department of Electronics Microelectronics Computer and Intelligent Systems Faculty of Electrical Engineering and Computing University of Zagreb Unska 3 HR-10000 Zagreb Croatia ECTM-DIMES Delft University of Technology Feldmannweg 17 2628 CT Delft Netherlands

ISBN: (纸本)9789532330670

A comprehensive study of hole mobility behavior with downscaling of silicon body thickness in single-gate ultrathin-body silicon-on-insulator MOSFETs on (100) surface is performed. We present a physics-based model that includes optical and acoustic phonon scattering, surface roughness scattering (including scattering induced by silicon thickness fluctuations) and Coulomb scattering. Although the model is based on effective mass approximation, comparison of simulation results and experimental data shows an excellent agreement, from 30 nm down to 3.8 nm-thick SOI pMOSFETs. © 2011 MIPRO.

关键词： Hole mobility

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Design for testability in nano-CMOS analog integrated circuits using a new design analog checker

Design for testability in nano-CMOS analog integrated circui...

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International SoC Design Conference, ISOCC

作者： Mouna Karmani Ka Lok Man Chiraz Khedhiri Belgacem Hamdi Electronics & Microelectronics Laboratory Monastir Tunisia Department of Computer Science and Software Engineering Xian Jiaotong-Liverpool University China and Myongji University South Korea Electronics & Microelectronics Laboratoary ISSAT Sousse Tunisia

In this paper, we focus on safety-critical applications based on the System-on-Chip (SoC) approach design and using the nano-CMOS (Complementary Metal Oxide Semiconductor) technology. These systems are present in diverse areas in our life from consumer electronic products to automobile, aerospace, medical, nuclear and military applications. These products could cause injury or loss of human life if they fail or encounter errors. In fact, the malfunctioning of these equipments can be much dangerous which needs special attention to ensure the functionality, quality and dependability of the product. Thus, dependability must be considered from the beginning when designing the system. Therefore, testing should even be considered earlier, intertwined with the design process. The process of designing for better testability is called design for testability (DfT). The first part of the paper presents a DfT technique using a new design analog checker circuit to assure the detection of defects occurring in nano-CMOS analog integrated circuits (ICs). The checker is implemented in full-custom 65nm CMOS technology at 1 V power supply. SPICE simulations of the post-layout extracted CMOS checker, which includes all parasitic, are used to validate the technique and demonstrate the acceptable electrical behaviour of the checke.

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Series switched resonator based dual-band oscillator

Series switched resonator based dual-band oscillator

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General Assembly and Scientific Symposium, URSI

作者： Vivek Sharma Ravinder Yadav N. P. Pathak Radio Frequency Integrated Circuit (RFIC) Research Group Electronics & Computer Engineering (ECE) Department Indian Institute of Technology Roorkee India

A series switched resonator based dual-band oscillator, employing single transistor, is reported. The oscillator employs a semiconductor diode, as switch, to change the resonator's effective length, thereby, controlling the oscillator's negative resistance to shift its output between two desired frequencies. Agilent's Advanced Design System (ADS) in conjunction with the electromagnetic simulation tool (EMDS) were used to design the oscillator. The measured characteristics of the fabricated dual-band oscillator, operating near 5.7 GHz and 6.48 GHz, indicate constant output power levels of 4.02 dBm with second harmonic power levels being at least 12 dB below. The measured characteristics also indicate -116.3 dBc/Hz and -95.23 dBc/Hz phase noise levels at 1 MHz offset for the above mentioned two cases, respectively.

关键词： Oscillators Resonant frequency Dual band Switches Microstrip Transistors Switching circuits

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New processor array architecture for scalable radix 8 montgomery modular multiplication algorithm

New processor array architecture for scalable radix 8 montgo...

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Canadian Conference on Electrical and computer engineering (CCece)

作者： Atef Ibrahim Fayez Gebali Hamed Elsimary Amin Nassar Department of Microelectronics Electronics Research Institute Cairo Egypt Department of Electrical and Computer Engineering University of Victoria Victoria BC Canada Department of Electronics and Electrical Communications Cairo University Cairo Egypt

This paper presents a new processor array architecture for scalable radix 8 Montgomery modular multiplication algorithm. In this architecture, the multiplicand and the modulus words are allocated to each processing element rather than pipelined between the processing elements as in the previous architectures extracted by ***. Moreover, the multi plier bits are fed serially to the first processing element of the processor array every odd clock cycle. By analyzing this architecture, we found that it has a better performance in terms of area, speed, and power consumption-than the previous radix 8 architecture extracted by ***.

关键词： Arrays Clocks Adders Delay Algorithm design and analysis Hardware

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Trimming lithography part II: An effect of trimming distance to the sub-resolution pattern quality

Trimming lithography part II: An effect of trimming distance...

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International Conference on Electrical engineering/electronics, computer, Telecommunications and Information Technology, ECTI-CON

作者： Arreerat Sriklat Nithi Atthi Wutthinan Jeamsaksiri Charndet Hruanun Amporn Poyai Rardchawadee Silapunt Department of Electronics and Telecommunication Engineering King Mongkut's University of Technology Thonburi Thailand Thai Microelectronics Center (TMEC) National Electronics and Computer Technology Center Thailand

Trimming lithography acts as one of the candidates for next generation lithography. The pattern size can be scaled by adjusting the trim distance that is much bigger than an original design linewidth. The photoresist feature size can be scaled down to 0.18 μm with the 0.9 μm mask and the 0.5 μm resolution exposure tool. However, a pattern density of the line/space pattern is lower than that of other patterning techniques. Different pattern qualities between dense and isolated patterns are explained by a diffraction of the waveform transmitted through the mask slit.

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The study on the effect of multi-level exposure technique to fabricate air bearing surface microstructure

The study on the effect of multi-level exposure technique to...

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International Conference on Electrical engineering/electronics, computer, Telecommunications and Information Technology, ECTI-CON

作者： Patama Pholprasit Nithi Atthi Thawat Thammabut Wutthinan Jeamsaksiri Charndet Hruanun Amporn Poyai Rardchawadee Silapunt Department of Electronics and Telecommunication Engineering King Mongkut's University of Technology Thonburi Thailand Department of Electronics and Telecommunication Engineering King Mongkut's University of Technology Thonburi Thai Microelectronics Center (TMEC) National Electronics and Computer Technology Center Thailand Thai Microelectronics Center (TMEC) National Electronics and Computer Technology Center (NECTEC) Western Digital (Thailand) Co. Ltd.

Many photolithography and etching steps for a fabrication of an Air Bearing Surface (ABS) structure which is responsible for the aerodynamic behavior of a read/write head make a significant impact to HDDs overall cost. To reduce a cost/time consuming, the ABS can be fabricated by a technique called "multi-level exposure". This technique focuses on the exposure by changing the TV light intensity after moving the stage to a new position until all positions are completely exposed. The exposed wafer is then developed and etched in a single step to form 3 levels of the ABS structure. The relation between the remaining photoresist (PR) film thickness and the singleand the double-exposure dose can be calculated by using the exponential equations with 95.8% and 91.5% correlation, respectively.

关键词： Films

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The deflection length and emitter width on sensitivity of magnetotransistor

The deflection length and emitter width on sensitivity of ma...

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IEEE International Conference on Nano/Micro Engineered and Molecular Systems (NEMS)

作者： Toempong Phetchakul Panyakorn Sottip Chana Leepattarapongpan Narichapan Penpondee Putapon Pengpad Arckom Srihapat Chandet Hruanun Amporn Poyai Department of Electronics Faculty of Engineering King Mongkut''s Institute of Technology Ladkrabang Bangkok Thailand Thai Microelectronics Center National Electronics and Computer Technology Center Chachoengsao Thailand

This paper presents a study of effect of deflection length and emitter width on sensitivity of magnetotransistor. The device has been fabrication on standard CMOS technology. It can detect magnetic field applied vertically to the chip. The structure consists of emitter (n-type), base (p-type) and collector (n-type) on silicon p-substrate. The device can sense magnetic field by Hall Effect theory and carrier deflection resulting to difference between base and collector current (ΔI CB ) related to magnetic field (B Z ) strength. From the experiment is comparing emitter width of 4, 5 and 10 micrometer at deflection length of 10 and 20 micrometer. The result shows that increase in injection emitter width cause to the sensitivity decreases and the deflection length of 20 micrometer is the best sensitivity. These results are very useful for developing the magnetotransistor for high sensitivity and performance.

关键词： Sensitivity Magnetic fields Magnetic devices Lorentz covariance Hall effect Magnetic circuits Magnetic tunneling

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