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Stable ^(85)Rb micro vapour cells:fabrication based on anodic bonding and application in chip-scale atomic clocks

Chinese Physics B 2010年第11期19卷 243-250页

作者：苏娟邓科郭等柱汪中陈兢张耿民陈徐宗 Key Laboratory for the Physics & Chemistry of Nanodevices School of Electronics Engineering & Computer SciencePeking University Institute of Quantum Electronics School of Electronics Engineering & Computer SciencePeking University Department of Microelectronics School of Electronics Engineering & Computer SciencePeking University

We describe the microfabrication of ^85Rb vapour cells using a glass-silicon anodic bonding technique and in situ chemical reaction between rubidium chloride and barium azide to produce Rb. Under controlled conditions, the pure metallic Rb drops and buffer gases were obtained in the cells with a few mm^3 internal volumes during the cell sealing process. At an ambient temperature of 90 ℃ the optical absorption resonance of ^85Rb D1 transition with proper broadening and the corresponding coherent population trapping （CPT） resonance, with a signal contrast of 1.5% and linewidth of about 1.7 kHz, have been detected. The sealing quality and the stability of the cells have also been demonstrated experimentally by using the helium leaking detection and the after-9-month optoelectronics measurement which shows a similar CPT signal as its original status. In addition, the physics package of chip-scale atomic clock （CSAC） based on the cell was realized. The measured frequency stability of the physics package can reach to 2.1 × 10^-10 at one second when the cell was heated to 100 ℃ which proved that the cell has the quality to be used in portable and battery-operated devices.

关键词： ^85Rb Micro vapour cell anodic bonding coherent population trapping chip-scale atomic clock frequency stability

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A parallel architecture for ray-tracing with an embedded intersection algorithm

A parallel architecture for ray-tracing with an embedded int...

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Alexandre S. Nery Nadia Nedjah Felipe M.G. França Lech Jozwiak LAM-Computer Architecture and Microelectronics Laboratory Systems Engineering and Computer Science Program COPPE Universidade Federal do Rio de Janeiro Brazil Department of Electrical Engineering-Electronic Systems Eindhovan University of Technology Netherlands Department of Electronics Engineering and Telecommunications-Faculty of Engineering Universidade do Estado do Rio de Janeiro (UERJ) Brazil

Real time rendering of three-dimensional scenes in Ray Tracing is a hard problem. However, parallel implementations have been enabling real time performance, as the algorithm can be highly parallelized. Thus, a custom parallel design in hardware is likely to achieve a good performance. In this paper, we further improve the GridRT architecture overall performance by embedding the ray-triangle intersection computation into the precessing elements that form the architecture. Low cost and high rendering performance are the main concerns in this novel design. The results show that the execution time of each intersection computation is reduced by at least 50%, while the area cost is practically unchanged or even reduced when compared to the original GridRT implementation.

关键词： Ray tracing Registers Equations USA Councils Mathematical model Parallel architectures

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Hardware Reuse in Modern Application-Specific Processors and Accelerators

Hardware Reuse in Modern Application-Specific Processors and...

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Euromicro Symposium on Digital System Design

作者： Alexandre S. Nery Lech Jozwiak Menno Lindwer Mauro Cocco Nadia Nedjah Felipe M.G. Franca LAM-Computer Architecture and Microelectronics Laboratory Systems Engineering and Computer Science Program COPPE Universidade Federal do Rio de Janeiro Brazil Department of Electrical Engineering-Electronic Systems Eindhoven University of Technology Netherlands Silicon Hive-Intel UMG Netherlands Department of Electronics Engineering and Telecommunications-Faculty of Engineering Universidade do Estado do Rio de Janeiro Brazil

Effective exploitation of the application-specific parallel patterns and computation operations through their direct implementation in hardware is the base for construction of high-quality application-specific (re-)configurable application specific instruction set processors (ASIPs) and hardware accelerators for modern highly-demanding applications. Although it receives a lot of attention from the researchers and practitioners, a very important problem of hardware reuse in ASIP and accelerator synthesis is clearly underestimated and does not get enough attention in the published research. This paper is an effect of an industry and academic collaborative research. It analyses the problem of hardware sharing, shows its high practical relevance, as well as a big influence of hardware sharing on the major circuit and system parameters, and its importance for the multi-objective optimization and tradeoff exploitation. It also demonstrates that the state-of-the-art synthesis tools do not sufficiently address this problem and gives several guidelines related to enhancement of the hardware reuse.

关键词： Hardware Resource management computer architecture Optimization Program processors Adders Delay

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Outage Probability and SER Analysis of Partial Relay Selection in Amplify-and-Forward MIMO Relay Systems

Outage Probability and SER Analysis of Partial Relay Selecti...

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IEEE Conference on Vehicular Technology (VTC)

作者： Fangxiang Wang Guodong Xie Hang Long Jianquan Wang Wengbo Wang Wenbin Guo Bin Wu Wireless Signal Processing and Network Laboratory Beijing University of Posts & Telecommunications China Department of Electronics Engineering and Computer Science Peking University China China Unicom Research Institute China Institute of Microelectronics of Chinese Academy of Sciences China

In this paper, we investigate a cooperative system consisting of one source-destination pair equipped with single antenna and L relays equipped with M antennas as wireless access points. We propose a new relay selection scheme for this system based on partial relay selection, where the best relay is selected according to the instantaneous and one-hop channel state information (CSI). We use maximal ratio combining (MRC) and maximal ratio transmitting (MRT) at relays to obtain the maximal achievable received signal-to-noise ratio (SNR). Close-form expressions for the outage probability and symbol error rate (SER) are derived. High SNR analysis is tightly approximated to explicitly characterize the diversity order and array gain. Monte Carlo simulations verify our analytical results. Results show that the diversity order increases with the antenna numbers at the selected relay according to M. For partial relay selection, two available relays are enough to get the array gain, and impacts of relay locations are also discussed in this paper.

关键词： Relays Signal to noise ratio Antennas Arrays Diversity reception Wireless communication Binary phase shift keying

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Experimental Characterization of the Reliability of 3-Terminal Dual-Damascene Copper Interconnect Trees

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MRS Online Proceedings Library 2011年第1期716卷 8131-8136页

作者： Gan, C. L. Thompson, C. V. Pey, K. L. Choi, W. K. Wei, F. Yu, B. Hau-Riege, S. P. Advanced Materials for Micro- and Nano- Systems Programme Singapore-MIT Alliance Singapore Department of Materials Science and Engineering Massachusetts Institute of Technology Cambridge USA National University of Singapore now with School of Electrical & Electronics Engineering Nanyang Technological University Nanyang Avenue Singapore Department of Electrical & Computer Engineering National University of Singapore Singapore Institute of Microelectronics San Jose USA Intel Corp. Hillsborough OR 97124 now with Lawrence Livermore National Laboratory Livermore USA

Electromigration experiments have been carried out on simple Cu dual-damascene interconnect tree structures consisting of straight via-to-via (or contact-to-contact) lines with an extra via in the middle of the line. As with Al-based interconnects, the reliability of a segment in this tree strongly depends on the stress conditions of the connected segment. Beyond this, there are important differences in the results obtained under similar test conditions for Al-based and Cu-based interconnect trees. These differences are thought to be associated with variations in the architectural schemes of the two metallizations. The absence of a conducting electromigrationresistant overlayer in Cu technology, and the possibility of liner rupture at stressed vias lead to significant differences in tree reliabilities in Cu compared to Al.

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computer cluster workload analysis

Computer cluster workload analysis

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33rd International Convention on Information and Communication Technology, electronics and microelectronics, MIPRO 2010

作者： Grudenic, I. Bakarcic, I. Bogunovic, N. Department of Electronics Microelectronics Computer and Intelligent Systems Faculty of Electrical Engineering and Computing University of Zagreb Unska 3 Zagreb Croatia

ISBN: (纸本)9789532330502

Performance of computer clusters is greatly affected by a nature of the submitted workload. Early characterization of different workload types allows for scheduler fine tuning as well as predictions on the system load. Statistical analysis and visual representation of the workload data provide valuable insight to the overall system utilization and may reveal potential bottlenecks and points for improvement. In this paper we describe important cluster job features and introduce a tool for statistical analysis and manipulation of the workload data that is a part of a cluster simulation and runtime prediction system.

关键词： Statistical methods

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Evaluation of embedded processor based BDD implementation

Evaluation of embedded processor based BDD implementation

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33rd International Convention on Information and Communication Technology, electronics and microelectronics, MIPRO 2010

作者： Ivošević, Danko Sruk, Vlado Department of Electronics Microelectronics Computer and Intelligent Systems Faculty of Electrical Engineering and Computing University of Zagreb Unska 3 Zagreb 10000 Croatia

ISBN: (纸本)9789532330502

Different strategies for implementation of computationally intensive applications in hardware are available today. The spectrum of implementations ranges from usage of standardized microprocessors to specially tailored hardware solutions. Available processor architectures range from general purpose type through processors with instruction set extensions to application-specific processors. On the other side, recent advances in design automation resulted in development of C-to-hardware compilers as a new strategy for application implementation in hardware. In this paper, we present and elaborate characteristics of hardware implementations of Binary Decision Diagrams (BDDs) application, used in many research and development areas, and especially in formal verification and computer-Aided Design (CAD) tools. For this application, processor architecture using C-to-hardware NISC toolset is manually tailored and compared with implementation approaches based on standard soft and hard processors. All these approaches are implemented and verified using FPGA Virtex-5 development board. Our results show that, besides code and compiler side optimizations, more significant improvements in total execution cycles count can be achieved when processor architecture side optimizations are included.

关键词： Binary decision diagrams

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Papr reduction for improving performance of OFDM system

Papr reduction for improving performance of OFDM system

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2010 IEEE International Conference on Communication Control and Computing Technologies, ICCCCT 2010

作者： Arasu, C. Vennila Hyanki, Puneet Sharma, H. Lakshman Lakshminarayanan, G. Lee, Moon Ho Ko, Seok-Bum Department of Electrical and Computer Engineering University of Saskatchewan Canada Department of Electronics Chonbuk National University Korea Republic of Department of ECE National Institute of Technology Tiruchirapalli India

ISBN: (纸本)9781424477692

Orthogonal frequency division multiplexing (OFDM) signals have a generic problem of high peak to average power ratio (PAPR) which is defined as the ratio of the peak power to the average power of the OFDM signal. The drawback of the high PAPR is that the dynamic range of the power amplifiers (PA) & digital-to-analog (D/A) converters required during the transmission and reception of the signal is higher. As a result, the total cost of the transceiver increases, with reduced efficiency. This paper includes an idea of the P APR constraint, along with the implementation and analysis of some specific algorithms for P APR reduction of the OFDM signals. All the P APR reduction algorithms are implemented and tested in the OFDM transceiver designed using Matlab. Analyzing some specific algorithms, we propose a novel algorithm by combining the subcarrier phase adjustment and linear combination of the time domain OFDM signals. Simulation results for a OFDM system employing Quadrature Amplitude Shift Keying (QASK) symbols and Quadrature Amplitude Modulation (QAM) can achieve a PAPR reduction of 5 dB. ©2010 IEEE.

关键词： Orthogonal frequency division multiplexing

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Random forest-based classification of heart rate variability signals by using combinations of linear and nonlinear features

Random forest-based classification of heart rate variability...

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12th Mediterranean Conference on Medical and Biological engineering and Computing, MEDICON 2010

作者： Jovic, Alan Bogunovic, Nikola Department of Electronics Microelectronics Computer and Intelligent Systems Faculty of Electrical Engineering and Computing University of Zagreb Unska 3 Zagreb HR-10000 Croatia

ISBN: (纸本)9783642130380

The goal of this paper is to assess various combinations of heart rate variability (HRV) features in successful classification of four different cardiac rhythms. The rhythms include: normal, congestive heart failure, supraventricular arrhythmia, and any arrhythmia. We approach the problem of automatic cardiac rhythm classification from HRV by employing several features' schemes. The schemes are evaluated using the random forest classifier. We extracted a total of 78 linear and nonlinear features. Highest results were achieved for normal/supraventricular arrhythmia classification (93%). A feature scheme consisting of: time domain (SDNN, RMSSD, pNN20, pNN50, HTI), frequency domain (Total PSD, VLF, LF, HF, LF/HF), SD1/SD2 ratio, Fano factor, and Allan factor features demonstrated very high classification accuracy, comparable to the results for all extracted features. Results show that nonlinear features have only minor influence on overall classification accuracy. © 2010 International Federation for Medical and Biological engineering.

关键词： Electrocardiograms

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VLSI architecture design and implementation for application specific CORDIC processor

VLSI architecture design and implementation for application ...

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2nd International Conference on Advances in Recent Technologies in Communication and Computing, ARTCom 2010

作者： Mandal, Amritakar Tyagi, K.C. Kaushik, Brajesh Kumar Electronic Engineering and Installation Unit New Delhi India Department of ECE Dev Bhoomi Institute of Technology Dehradun India Department of Electronics and Computer Engineering Indian Institute of Technology Roorkee India

ISBN: (纸本)9780769542010

COordinate Rotation DIgital computer (CORDIC) algorithm has become widely researched topic in the field of vector rotated Digital Signal Processing (DSP) applications due to its simplicity. In this paper, we have represented the design of pipelined architecture for the computation of Sine and Cosine values based on application specific CORDIC processor. The design of CORDIC in the circular rotation mode gives a high system throughput due to its pipelined architecture by reducing latency in each individual pipelined stage. Saving area on silicon substrate is essential to the design of pipelined CORDIC and that can be achieved through the optimization in the number of micro rotations. The computed quantization error is also minimized using required number of iterations. The pipelined architecture can be easily integrated in VLSI technology due to its regularity and modularity. © 2010 IEEE.

关键词： Digital signal processing

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