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A microstrip ring-like diplexer for bluetooth and UWB application

Microwave and Optical Technology Letters 2009年第6期51卷 1518-1520页

作者： Ye, Chang-Sin Su, Yan-Kuin Weng, Min-Hang Hung, Cheng-Yuan Department of Electrical Engineering Advanced Optoelectronic Technology Center Institute of Microelectronics Taiwan National Nano Device Laboratories Hsin-Chu Taiwan Department of Electronics Engineering and Computer Sciences Tung-Fang Institute of Technology Hsin-Chu Taiwan

In this article, design of a microstrip ring-like diplexer for Bluetooth and ultrawide band application is presented. Two ring-like bandpass filters, operated at 2.4 and 4 GHz, are combined together to form the proposed microstrip diplexer. Several transmission zeros located at the passband edges are introduced to improve the passband selectivity. High isolation between the two passband greater than 28 dB is achieved in this study. The designed diplexer is investigated numerically and experimentally. Measured results show a good agreement with the simulated analysis. © 2009 Wiley Periodicals, Inc.

关键词： Bandpass filters

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Implantation-induced defects analysis base on activation energy diagnostics

Implantation-induced defects analysis base on activation ene...

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International Symposium on Integrated Circuits (ISIC)

作者： Weera Pengchan Toempong Phetchakul Amporn Poyai Department of Electronics Faculty of Engineering King Mongkut's Institute of Technology Ladkrabang Bangkok Thailand Thai MicroElectronics Center (TMEC) National Electronics and Computer Technology Center Chachoengsao Thailand

Low power consumption device can be realized by low junction leakage current. This leakage current relates to the defects in the depletion region of p-n junction. Among variety process steps, implantation step may generate defects. Therefore, the implantation-induced defects have been studied from the activation energy which has been obtained from the leakage current of p-n junction. The different geometry p-n junctions have been fabricated by a standard CMOS technology. The current-voltage (I-V) and high frequency capacitance-voltage (C-V) characteristics of p-n junctions with temperature dependence have been measured. The electrically active defects from implantation process can be extracted from the junction generation current density versus temperature. Base on this analysis, it will be demonstrated that the implantation-induced defects have been found in p+-n-well more than in n+-p-substrate. Finally, the possible nature of the defect will be discussed.

关键词： P-n junctions Leakage current CMOS technology Capacitance-voltage characteristics Energy consumption Geometry Frequency Temperature dependence Capacitance measurement Current measurement

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Multiplication of photocurrent in silicon planar metal-semiconductor-metal structures

Multiplication of photocurrent in silicon planar metal-semic...

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International Conference on Electrical engineering/electronics, computer, Telecommunications and Information Technology, ECTI-CON

作者： S. Khunkhao W. Titiroongruanga S. Niemcharoen A. Ruangphanit N. Phongphanchanthra Kazunori Sato Department of Electrical Engineering Sripatum University Bangkok Thailand Faculty of Engineering king Mongkut's Institute of Technology Ladkrabang Bangkok Thailand Thai Microelectronics Center National Electronics and Computer Technology Center Mueang Chachoengsao Chachoengsao Thailand National Electronics and Computer Technology(NECTEC) Thai Microelectronics Center(TMEC) Muang Chachoengsao Chachoengsao Thailand Department of Electronics Tokai University Hiratsuka Kanagawa Japan

DC photocurrent gain properties of planar metal-semiconductor-metal (MSM) optical sensor structures on have been investigated experimentally. The test structure has two co-planar Mo/n-Si Schottky-barrier junctions on silicon of resistivity 9-12 Omega-cm and the electrode separation is 20 mum. The current-voltage (I-V) characteristics measurements under illumination in visible range showed a rapid increase in photocurrent at higher biases examined. From the temperature, the dependence of I-V characteristics and noise measurements, such photocurrent increase was ascribes to avalanche multiplication of carriers photogenerated in the Schottky junction reversed-biased. From low-frequency (10-50 kHz) signal measurements, it was found that multiplication factor larger than 100 at 10 kHz and 30 at 50 kHz was achieved.

关键词： Photoconductivity Silicon Optical sensors Testing Conductivity Electrodes Current measurement Lighting Temperature dependence Noise measurement

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Effects of phosphorus implantation on the activation of magnesium doped in GaN

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Japanese Journal of Applied Physics 2009年第8 PART 1期48卷 0810031-0810034页

作者： Liu, Kuan-Ting Chang, Shoou-Jinn Wu, Sean Department of Electronic Engineering Cheng Shiu University No. 840 Chengcing Road Kaohsiung County 833 Taiwan Institute of Microelectronics Department of Electrical Engineering National Cheng Kung University 1 University Road Tainan 701 Taiwan Department of Electronics Engineering and Computer Sciences Tung-Fang Institute of Technology 110 Tung-Fung Road Hunei Shiang Kaohsiung 829 Taiwan

The effects of phosphorus implantation on the activation of magnesium doped in GaN at different dopant concentration ratios have been systematically investigated. Hall effect measurements show that P implantation improves the hole concentration, and that this improvement is dependent on P/Mg dopant concentration ratio and annealing conditions. This phenomenon is attributable to the reduction in selfcompensation that results from the formation of deep donors and the enhanced Mg atom activation, which is in reasonable agreement with the optical properties observed by photoluminescence measurements. In addition, a new photoluminescence peak resulting from P-related transitions is also observed, evidently owing to the recombination of electrons from the shallow native donors with holes previously captured by isoelectronic P traps. © 2009 The Japan Society of Applied Physics.

关键词： Chemical activation

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Influence of polysilicon thickness on the microwave attenuation losses of the CPWs fabricated on polysilicon-passivated high-resistivity silicon substrates

Influence of polysilicon thickness on the microwave attenuat...

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International Symposium Semiconductor Device Research (ISDRS)

作者： Chao-Jung Chen Ruey-Lue Wang Yan-Kuin Su Chun-Yuan Huang Yung-Feng Chen Cheng-Yuan Hung Advanced Optoelectronic Technology Center Institute of Microelectronics and Department of Electrical Engineering National Cheng Kung University Tainan County Taiwan Department of Electrical Engineering National Kaohsiung Normal University Kaohsiung Taiwan Department of Applied Science National Taitung University Taitung Taiwan Department of Electronics Engineering and Computer Science Tung Fang Institute of Technology Taiwan

In this paper, the microwave performance of coplanar waveguides (CPWs) fabricated on high-resistivity silicon (HRS) substrates with various polysilicon film thicknesses was investigated. CPWs were fabricated on p-type silicon substrates with resistivities of 6000-8000 ¿-cm. Polysilicon films with thicknesses ranging from 100 to 900 nm were deposited by LPCVD, in which a 300 nm-deposited polysilicon was generally used as surface passication layer on the HRS substrates. Subsequently, the oxide layer was deposited on the polysilicon layer by PECVD, and a pure aluminum film was evaporated and patterned to form the 50-¿-CPW test structures. The CPWs were characterized through S-parameter measurements for up to 40 GHz by using an HP-8510 network analyzer. Experimental results show that the microwave attenuation loss can be influenced by a small variation of polysilicon layer thickness, especially when the thickness is smaller. Thicker polysilicon layers lead to higher grain boundary density, hence, free carriers can be rapidly trapped within grain boundary interfaces of the polysilicon, and the surface recombination velocity can be enhanced, thus, reducing the conductivity and bias-dependence of the surface layers. Furthermore, the bias effect on the HRS with various polysilicon thicknesses was taken into account as well.

关键词： Attenuation Silicon Substrates Conductivity Grain boundaries Coplanar waveguides Semiconductor films Aluminum Testing Scattering parameters

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A massively parallel hardware architecture for ray-tracing

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International Journal of High Performance Systems Architecture 2009年第1期2卷 26-34页

作者： Nery, A.S. Nedjah, N. França, F.M.G. Computer Architecture and Microelectronics Laboratory Systems Engineering and Computer Science Program COPPE P.O. Box 68511 21941-972 Rio de Janeiro Brazil Department of Electronics Engineering and Telecommunications Faculty of Engineering Universidade do Estado do Rio de Janeiro Rua Sao Francisco Xavier 524 Sala 5145-F Maracana 20.550-900 Rio de Janeiro RJ Brazil Universidade Federal do Rio de Janeiro Rio de Janeiro Brazil Department of Electronics Engineering and Telecommunications Faculty of Engineering State University of Rio de Janeiro Brazil Brazil

Real time performance of non-interactive rendering of three-dimensional scenes is usually unachievable. Ray tracing is one of the methods used for rendering such scenes. The performance achieved by a sequential software-based implementation of ray tracing is far from satisfactory. In contrast, many parallel implementations of ray tracing have been enabling real time performance, as the underlying algorithm can be massively parallelised. Thus, it is expected that a custom parallel design in hardware is likely to achieve the acceptable performance standards. In this paper, we propose a hardware architecture, which we call GridRT, capable of dealing with the main desirable features of ray tracing, such as shadows and reflections effects, imposing low requirements in terms of silicon area while achieving acceptable performance in terms of rendering time. This architecture achieves is efficient yet compact as it explores the massive parallelism offered by the intrinsic structure of the algorithm. The design exploits the usage the spatial data structure of regular grids. Copyright © 2009 Inderscience Enterprises Ltd.

关键词： Ray tracing

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Analog layout synthesis - Recent advances in topological approaches 09

Analog layout synthesis - Recent advances in topological app...

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Design, Automation and Test in Europe Conference and Exhibition

作者： H. Graeb F. Balasa R. Castro-Lopez Y.-W. Chang F.V. Fernandez P.-H. Lin M. Strasser Institute of EDA Technische Universitat Munchen Germany Department of Computer Science and Information Systems Southern Utah University USA Institute of Microelectronics of Seville CSIC and University of Sevilla Spain Graduate Institute of Electronics Engineering National Taiwan University Taiwan

ISBN: (纸本)9783981080155

This paper gives an overview of some recent advances in topological approaches to analog layout synthesis and in layout-aware analog sizing. The core issue in these approaches is the modeling of layout constraints for an efficient exploration process. This includes fast checking of constraint compliance, reducing the search space, and quickly relating topological encodings to placements. Sequence-pairs, B*-trees, circuit hierarchy and layout templates are described as advantageous means to tackle these tasks.

关键词： Shape Electronic design automation and methodology Simulated annealing Circuit synthesis Genetic algorithms Tree graphs computer science Information systems microelectronics Encoding

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An experimental 0.6-V 57.5-fJ/conversion-step 250-kS/s 8-bit rail-to-rail successive approximation ADC in 0.18µm CMOS

An experimental 0.6-V 57.5-fJ/conversion-step 250-kS/s 8-bit...

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IEEE International Conference on electronics, Circuits and Systems (ICECS)

作者： Christian Fayomi Gilson I. Wirth David Binkley Akira Matsuzawa Computer Science Department UQAM Microelectronics Laboratory Montreal QUE Canada Departamento de Engenharia Elétrica Federal University of Rio Grande do Sul Porto Alegre Rio Grande do Sul Brazil Department of Electrical and Computer Engineering North Carolina State University Charlotte NC USA Department of Physical Electronics Tokyo Institute of Technology Japan

ISBN: (纸本)9781424450909;9781424450916

An experimental 0.6-V 57.5-fJ/conversion-step 250-kS/s 8-bit rail-to-rail successive approximation (SA) analog-to-digital converter (ADC) implemented in a standard CMOS 0.18 μm digital process is presented. To overcome the input sampling switches limitation imposed by the low supply voltage we make use of a track-and-hold circuit based on a low-voltage, low-stress and reliable clock signal with a novel rail-to-rail track-and-latch comparator circuit. Power and area saving are achieved using splitarray charge redistribution-based SA ADC. Successive approximation and control logic is implemented using a robust single clock phase D flip-flop. Preliminary simulation results show that the ADC consumes only 3.68 μW.

关键词： Clocks Analog-digital conversion CMOS process Signal sampling Switching circuits Switches Low voltage Rail to rail inputs Logic Robust control

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Investigating the Effects of Different Gate Biasing Voltages and Temperatures on RadFETs

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ECS Transactions 2009年第1期18卷

作者： Hao Tang Yichen Liu Yi Wang Jinyan Wang Yufeng Jin Department of Electronics Engineering and Computer Science Peking University Institute of Microelectronics Peking University 5 Yiheyuan Road Beijing Beijing 100871 China Institute of Microelectronics Peking University

This paper mainly focuses on the effects of different gate biasing voltages and temperatures on several kinds of RadFETs. Four kinds of gate biasing configurations (positive, zero, negative gate voltage and continuous current applied model) have been compared in terms of sensitivity to radiation. Post-irradiation characteristics of annealing or fading under different gate biasing voltages and temperatures are also studied. Samples irradiated by zero and negative voltage biasing have lower sensitivity than that of positive, but don't show significant fading. It is presented that higher temperature can promote the process of annealing.

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Development of micromachined silicon accelerometers with improved off-axis sensitivity

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International Journal of COMADEM 2008年第1期11卷 18-24页

作者： Sankar, A. Ravi Das, S. Kal, S. Advanced Technology Centre E and ECE Dept. Indian Institute of Technology Kharagpur - 721302 India Electronics and Electrical Communication Engineering IIT Kharagpur Advanced Technology Centre IIT Kharagpur Microelectronics Center of I.I.T. Kharagpur Department of Electronics and ECE Institution of Engineers India IEEE United States Advanced Technology Centre of IIT Kharagpur

Development of micromachined silicon piezorcsistive accelerometers with improved off-axis sensitivity has been presented in this paper. Two accelerometer structures have been designed for low off-axis sensitivity. Complete comparative analysis based on simulation results has been given in this paper. Both the structures have been fabricated and testing results of structure-1 have been presented. The fabrication accelerometers involved three wafer levels and seven masking processes. Five masks were used for realizing piezoresistive sensing element and two masks were used for pyrex wafer processing which contains top and bottom cover lids for both the structures to provide squeeze film damping mechanism. In the fabrication process, dual doped TMAH solution is used for wet anisotropic etching. The novelty of this etching process is that the bulk micromachining can be performed after aluminum metallization. The fabrication process is CMOS compatible. © 2008 COMADEM International.

关键词： Accelerometers

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