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computer simulation of germanium nanowire field effect transistors

Computer simulation of germanium nanowire field effect trans...

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2005 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2005

作者： Li, Yiming Chou, Hung-Mu Lee, Bo-Shian Lu, Chien-Sung Yu, Shao-Ming Department of Communication Engineering National Chiao Tung University P.O. Box 25-178 1001 Ta-Hsueh Hsinchu 300 Taiwan Microelectronics and Information Systems Research Center National Chiao Tung University P.O. Box 25-178 1001 Ta-Hsueh Hsinchu 300 Taiwan Department of Electrical Engineering National Central University P.O. Box 25-178 1001 Ta-Hsueh Hsinchu 300 Taiwan Institute of Electronics National Chiao Tung University P.O. Box 25-178 1001 Ta-Hsueh Hsinchu 300 Taiwan Department of Computer and Information Science National Chiao Tung University P.O. Box 25-178 1001 Ta-Hsueh Hsinchu 300 Taiwan

ISBN: (纸本)4990276205

In this paper, electrical characteristics of germanium (Ge) nanowire field effect transistors (FETs) are computationally investigated. A calibrated three-dimensional (3D) density-gradient simulation is performed to explore the electrical characteristics of Ge omega-shaped-gate FETs. The examined nanodevices are with a 70% gate coverage ratio. By evaluating the threshold voltage roll-off, the transfer characteristics, and the leakage current, our numerical results have shown that the Ge nanowire FET has potentially higher driving-capability than that of the silicon (Si) one. Due to good channel controllability of the omega-shaped-gate FET with the 70% gate coverage ratio, compared with the Si nanowire FET, the high mobility Ge nanowire FET significantly suppresses the effect of band-gap narrowing on the transport characteristics. Leakage current of the Ge nanowire FET depends upon the thickness of the gate channel film. A thinner Ge film leads to a lower leakage current. Preliminary numerical study on the Ge Nanowire FET with a propoer selection on gate material provides interesting results for the design and fabrication of high performance nanodevices in nanoelectronics era.

关键词： Field effect transistors

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Active system identification of a DC-DC converter using digital control

Active system identification of a DC-DC converter using digi...

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Collection of Technical Papers - 2nd International Energy Conversion engineering Conference

作者： Zane, Regan Miao, Botao Maksimovic, Dragan Colorado Power Electronics Center ECE Department Univeristy of Colorado Boulder United States Department of Electrical and Computer Engineering UCB 425 United States

ISBN: (纸本)1563477157

A technique has been developed to actively identify the open-loop characteristics of a DC-DC converter while the unit operates. A digital controller is used to perform both the closed-loop control of the converter and to periodically identify the "plant" using a pseudo-random digital signal. Experimental results are provided for a digitally controlled 90W forward converter to demonstrate accurate and effective identification of the converter control-to-output dynamic response. Hardware requirements and potential fast algorithms are discussed for implementing the real-time converter regulation and identification operations. Copyright© 2004 by the American Institute of Aeronautics and Astronautics, Inc. All rights reserved.

关键词： Power converters

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Increasing the efficiency of three terminal silicon CMOS LED's through current density and carrier injection techniques

Increasing the efficiency of three terminal silicon CMOS LED...

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IEEE International Symposium on Electron Devices for Microwave and Optoelectronic Applications, EDMO 2004

作者： Snyman, Lukas W. Matjila, Jerry M. Aharoni, Herzl Du Plessis, Monuko Department of Electronic Engineering French South African Technical Institute in Electronics Tshwane University of Technology 0002 South Africa Carl and Emily Fuchs Institute for Microelectronics Department of Electrical Electronic and Computer Engineering University of Pretoria 0002 Pretoria South Africa Carl and Emily Fuchs Institute for Microelectronics Department of Electrical and Computer Engineering Beer-Sheva 84105 Israel

In this paper we will report on the dependency of quantum efficiency of an avalanching light emitting junction on the current from an adjacent lying forward biased junction. The phenomenon is observed in a three terminal silicon CMOS bipolar junction light emitting device (Si CMOS BJT LED). Our observations show that the overall quantum efficiency and light emission from these type of devices can be improved to the NQ=10-4 regime. The device has the potential of being fully integratable with any standard CMOS integrated circuitry with no adaptation to the CMOS design and processing procedures and light emissions can be confined to submicron dimensions. The optical emissions is about four orders higher than the low frequency detectivity for silicon CMOS detectors of comparable dimension. Our two junction, three terminal device also enable modulation of the light emission by a third terminal contact while using two terminals for biasing. The reverse bias avalanche configuration of the avalanching light emitting junction offers modulation capabilities of the device to within the GHz range. © 2004 IEEE.

关键词： Light emitting diodes

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Schottky s/d MOSFETs with high-Kgate dielectrics and metal gate electrodes

Schottky s/d MOSFETs with high-Kgate dielectrics and metal g...

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2004 7th International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT 2004

作者： Zhu, Shiyang Chen, Jingde Yu, H.Y. Whang, S.J. Chen, J.H. Shen, C. Li, M.F. Lee, S.J. Zhu, Chunxiang Chan, D.S.H. Du, Anyan Tung, C.H. Singh, Jagar Chin, Albert Kwong, D.L. Silicon Nano Device Lab. Dept. of ECE National University of Singapore Singapore 119260 Institute of Microelectronics Singapore 117685 Dept. of Microelectronics Fudan University Shanghai 200433 China Dept. of Electronics Engineering National Chiao Tung University Hsinchu 300 Taiwan Dept. Electrical and Computer Eng. Univ. of Texas Austin TX 78712 United States

Bulk Schottky suicide source/drain n- and p-MOS transistors (SSDTs) with EOT=2.0-2.5nm HfO2 gate dielectric and HfN/TaN metal gate have been successfully demonstrated using a low temperature process. P-SSDTs with PtSi suicide show excellent electrical performance of Ion ∼10 7-108 and subthreshold slop of 66 mV/dec. N-SSDTs with YbSi2-x silicide have also demonstrated a very promising characteristic with a recorded high Ion/Ioff radio of∼ 107 and subthreshold slope of 75mV/dec. To the best of our knowledge, these are the best SSDTs data reported so far. The implant free low temperature process relaxes the thermal budget of high-K dielectric and metal gate materials. Our results are expected to be further improved when using ultra-thin-body (UTB) SOI structures, -showing great potential of this low temperature process SSDTs for future sub-tenth micron CMOS technology. © 2004 IEEE.

关键词： Electrodes

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Simulation of multi-robot reinforcement learning for box-pushing problem

Simulation of multi-robot reinforcement learning for box-pus...

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Mediterranean Electrotechnical Conference (MELECON)

作者： K. Kovac I. Zivkovic B.D. Basic Computer and Intelligent Systems Faculty of Electrical Engineering and Computing Department of Electronics Microelectronics University of Zagreb Zagreb Croatia

The box-pushing problem represents a challenging domain for the study of object manipulation in a multi-robot environment. Our box-pushing problem is based on the pusher-watcher approach, involving two pushers robots that learn the best strategy for cooperatively moving an oversized elongated box to a specified goal and one watcher robot acting as the environment. This paper presents a solution to the box-pushing problem based on reinforcement learning in a multi-agent system. Within the framework of the paper, a simulator has been developed to carry out the practical tests.

关键词： Learning Robot kinematics Multiagent systems Testing Orbital robotics Robot sensing systems Service robots Infrared detectors Computational modeling microelectronics

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Gradient of B-splines in volume rendering

Gradient of B-splines in volume rendering

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Mediterranean Electrotechnical Conference (MELECON)

作者： Z. Mihajlovic L. Budin J. Radej Faculty of Electrical Engineering and Computing Department of Electronics Microelectronics Computer and Intelligent Systems University of Zagreb Zagreb Croatia

This paper deals with surface reconstruction and the gradient reconstruction in the volume rendering. In the volume rendering procedure, reconstruction according to the discrete set of samples is required. Due to the reconstruction procedure alias artifacts in the final image, it could not be neglected. In this paper, we focus our attention on the gradient reconstruction based on the surface reconstruction. For the surface reconstruction we use the cubic B-splines and for the gradient reconstruction corresponding derivative. If the noise is present in the input data, the approximation of B-spline is used, and the interpolation B-spline is used for the input signal without the noise. The shading procedure requires normal estimation. Two approaches are used for normal estimation. The classic approach for normal estimation is central difference calculation, and we propose derivative calculation of the reconstruction B-spline function. We show that the calculation of the normal vector has important influence on the alias artifacts in the result.

关键词： Spline Image reconstruction Surface reconstruction Data visualization Rendering (computer graphics) Interpolation Lighting Filters microelectronics Intelligent systems

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WODLS - a Web oriented distance learning system

WODLS - a Web oriented distance learning system

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Mediterranean Electrotechnical Conference (MELECON)

作者： V. Glavinic M. Cupic S. Gros Department of Electronics Microelectronics Computer and Intelligent Systems Faculty of Electrical Engineering and Computing University of Zagreb Zagreb Croatia

Present-day educational activities heavily rely on an increasing inclusion of computer systems to support the process of learning and teaching. In the existing variety of such systems the emphasis is usually given to some sort of student self-study leading to different forms of asynchronous educational systems (e.g. intelligent tutoring systems), while on the other hand the area of direct support to existing teaching forms remains somewhat less covered. In this paper we describe the Web oriented distance learning system - WOOLS, a system we developed to support the lab exercises for a sophomore level course in Digital electronics with an abundant number of enrolled (about 600) students. We describe the new organization of the lab exercises for the course as well as the implications for students' evaluation. We also explain the objectives that led to WODLS's development, and provide insight into its functionality, architecture and user interface. Finally we comment on the results of using WODLS in "live" lab exercises and explain some lessons learned.

关键词： computer aided instruction Education Intelligent systems Educational activities microelectronics computer architecture User interfaces Laboratories Communications technology Hardware

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Selected topics on HfO/sub 2/ gate dielectrics for future ULSI CMOS devices

Selected topics on HfO/sub 2/ gate dielectrics for future UL...

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International Conference on Solid-State and Integrated Circuit Technology

作者： M.F. Li H.Y. Yu Y.T. Hou J.F. Kang X.P. Wang C. Shen C. Ren Y.C. Yeo C.X. Zhu D.S.H. Chan A. Chin D.L. Kwong Silicon Nano Device Laboratory ECE Department National University of Singapore Singapore Institute of Microelectronics Peking University Beijing China Department Electronics Engineering National Chiao Tung University Hsinchu Taiwan Microelectronics Research Center Department ECE University of Technology Austin TX USA

Based on our recent investigation on HfO/sub 2/ high-k gate dielectrics, we review the Hf based gate dielectric in the future ULSI CMOS devices in the following aspects: How long HfO/sub 2/ can be used satisfactorily, assessed from the gate tunneling and scalability; how thin EOT can be grown technologically assessed by interfacial layer thickness; and how high operating voltage can be employed for 10 years reliable operation, assessed by charge trapping and threshold voltage shift.

关键词： Hafnium oxide Dielectric devices Ultra large scale integration Gate leakage Tunneling Leakage current Artificial intelligence CMOS technology Tires Electrons

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Multiple scan tree design with test vector modification

Multiple scan tree design with test vector modification

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Asian Test Symposium (ATS)

作者： K. Miyase S. Kajihara S.M. Reddy Department of Computer Sciences and Electronics Kyushu Institute of Information Sciences Japan Department of Computer Sciences and Electronics Center for Microelectronics Systems Kyushu Institute of Information Sciences Japan Department of Electrical and Computer Engineering University of Iowa USA

In this paper, we propose a method of test compression for multiple scan designs. Instead of the conventional serial scan chains, the proposed method constructs scan trees in which scan flip-flops are placed and routed in a tree structure. Inputs of the scan trees drive several scan trees of different lengths (height). Since test data volume and test application time are dominated by the scan tree with the maximum height among the constructed scan trees, the proposed method distributes the scan flip-flops to the scan trees so as to minimize the maximum height of the scan trees. In addition, the proposed method modifies the given test vectors to maximize the reduction in test application time. Experimental results for ISCAS-89 benchmark circuits show that the proposed method could reduce, on the average, test data volume by 77% compared with the conventional multiple scan design. The scan tree construction enlarges the number of scan outputs required. However test data volume could be reduced by 66% even if the number of scan outputs is limited.

关键词： Circuit testing Flip-flops Electronic equipment testing Tree data structures Fault detection Tree graphs microelectronics System testing Benchmark testing Design methodology

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Effects of barrier height (/spl Phi//sub B/) and the nature of bi-layer structure on the reliability of high-k dielectrics with dual metal gate (Ru & Ru-Ta alloy) technology

Effects of barrier height (/spl Phi//sub B/) and the nature ...

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Symposium on VLSI Technology

作者： Y.H. Kim R. Choi R. Jha J.H. Lee V. Misra J.C. Lee Microelectronics Research Center Department of Electrical and Computer Engineering University of Technology Austin TX USA Department of ECE North Carolina State University Raleigh NC USA

In this work, we present the effects of barrier height on the reliability of HfO/sub 2/ with dual metal gate technology in terms of Weibull slope, soft breakdown characteristics, defect generation rate, critical defect density and charge-to-breakdown. It was found that the lower Weibull slope of high-k dielectrics (compared to SiO/sub 2/) is partially attributed to the lower barrier height of high-k dielectrics which in turn results in larger current increase. Thus, defect generation rate increases and charge-to-break down decreases, while critical defect density remains constant. In addition, it has been found that there is distinct bi-modal defect generation rate for high-k/SiO/sub 2/ stack. Two-step breakdown process was clearly observed; and Weibull slope of soft breakdown (1/sup st/ breakdown) shows lower /spl beta/ value compared to that of hard breakdown (2/sup nd/ breakdown). Soft breakdown characteristics were dependent on the barrier heights. The bi-modal defect generations are believed to be resulted from the breakdown in interface and bulk layer.

关键词： High-K gate dielectrics Electric breakdown Electrodes High K dielectric materials Leakage current Stress Hafnium oxide Dielectric substrates Character generation Thickness control

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