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13th International Conference on Solid-State Sensors, Actuators and Microsystems

作者： Liu, F Yang, C Ren, TL Liu, LT Feng, HG Wang, AZ Long, HB Yu, J Institute of Microelectronics Tsinghua University China Institute of Microelectronics Huazhong University of Science and Technology China Integrated Electronics Laboratory Department of ECE Illinois Institute of Technology United States Department of Electronic Engineering Tsinghua University China

ISBN: (纸本)0780389948

Ferrite thin-film RF integrated inductors using IC compatible processes are proposed firstly. Ferrites (Co-based, CoFe-based, MnZn-based, NiZn-based and garnet) for RF integrated inductors are investigated, and CoZrO shows the suitable high-frequency performance for RF applications. Various inductors with different kinds of ferrite thin-films have been fabricated using fully integrated processes. A typical inductor sample with CoZrO thin-film is presented. The L and Q values of the sample are 2.05nH and 20.5 at 2GHz, respectively. The inductance is raised by 17% and the quality factor is raised by 41%, compared with the inductor, which doesn't include ferrite thin-film. With the improvement of L and Q, the size of ferrite thin-film inductors can be reduced significantly.

关键词： inductor ferrite fully integration RF ICs

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Nescume - A system for managing student assignments

Nescume - A system for managing student assignments

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1st International Conference on Internet Technologies and Applications, ITA 05

作者： Glavinić, Vlado Čupić, Marko Groš, Stjepan Faculty of Electrical Engineering and Computing Department of Electronics Microelectronics Computer and Intelligent Systems University of Zagreb Zagreb Croatia

ISBN: (纸本)0946881324

This paper describes Nescume -a Web enabled package for managing student (lab) assignments. The package has been designed targeting a number of requirements met in teaching software-based courses. The paper discusses objectives for Nescume development, presents its capabilities such as source code comparison for cheating detection, testing of developed program and source code archiving, and shows its architecture. Furthermore, the paper explains how the system can be used to improve both the course as well as students quality. Integration with the course management software is also considered, as illustrated by the WODLS package.

关键词： Students

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VPart: An automatic partitioning tool for dynamic reconfiguration

VPart: An automatic partitioning tool for dynamic reconfigur...

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ACM/SIGDA Thirteenth ACM International Symposium on Field Programmable Gate Arrays - FPGA 2005

作者： Kafka, Leos Kielbik, Rafal Matousek, Rudolf Moreno, Juan Manuel Institute of Information Theory and Automation CAS Prague Czech Republic Department of Microelectronics and Computer Science Technical University of Lodz Lodz Poland Department of Electronics Engineering Technical University of Catalunya Barcelona Spain

This paper presents an innovative tool for automatic partitioning of VHDL designs for dynamic reconfiguration called VPart. An introduction to the dynamic implementation of a circuit is presented. A design flow and optimization algorithms and methods used by the tool to partition the input design are explained. The usage of the tool is shown on three simple experiments performed on 18-bit floating-point arithmetic adder and multiplier.

关键词： Integrated circuit layout

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Appointments for 2005-2006 term

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IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2005年第7期13卷 773-782页

作者： Ranganathan, Nagarajan Agrawal, Vishwani D. Chakradhar, Srimat T. Chakrabarty, Krishnendu Courtois, Bernard DeMara, Ronald Hu, Xiaobo Sharon Ismail, Yehea I. Jha, Niraj K. John, Lizy Kurian Ker, Ming-Dou Koren, Israel Liu, Bin-Da Marculescu, Diana Marculescu, Radu Narayanan, Vijaykrishnan Nassif, Sani R. Nowick, Steven M. Sapatnekar, Sachin S. Sherlekar, Sunil Sylvester, Dennis Vemuri, Ranga Pham, Michael Department of Computer Science and Engineering University of South Florida Tampa FL 33620 United States Department of Computer Science and Engineering Nanomaterials and Nanomanufacturing Research Center University of South Florida Tampa United States IEEE United States Systems United States Department of Electrical and Computer Engineering Rutgers University New Brunswick NJ United States IETE India ACM NEC Laboratories America Inc. Princeton NJ United States Duke University Durham NC United States ACM SIGDA Sigma Xi United States Laboratory of Techniques of Informatics and Microelectronics for Computer Architectecture ASME IMAPS IEEE Computer Society University of Central Florida Orlando United States Computer Engineering Program SEECS Department of Computer Science and Engineering University of Notre Dame Notre Dame IN United States Northwestern University Evanston IL United States Department of Electrical Engineering Princeton University Princeton NJ United States Association for Computing Machinery Austin United States UT Austin Engineering Foundation United States Department of Electronics Engineering National Chiao-Tung University Taiwan Department of Electrical and Computer Engineering University of Massachusetts Amherst United States Department of Electrical Engineering Department of Electrical and Computer Engineering Carnegie Mellon University Pittsburgh PA United States Electrical and Computer Engineering Faculty Carnegie Mellon University Pittsburgh PA United States Computer Science and Engineering Department Pennsylvania State University University Park United States IBM Austin Research Laboratory Austin TX United States Columbia University New York NY United States Department of Electrical and Computer Engineering University of Minnesota Minneapolis United States Tata Consultancy Services Centre of Excellence for Embedded Systems India Department of Electrical Engineering IIT Bombay India Department of Electrical Engineering Uni

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Design, fabrication, testing and simulation of porous silicon based smart MEMS pressure sensor

Design, fabrication, testing and simulation of porous silico...

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International Conference on VLSI Design

作者： C. Pramanik T. Islam H. Saha J. Bhattacharya S. Banerjee S. Dey IC Design and Fabrication Centre Department of Electronics & Telecommunication Engineering Jadavpur University Kolkata India Department of ECE Indian Institute of Technology Kharagpur India Microelectronics Research Centre Department of ECE University of Technology Austin USA

Porous silicon based piezoresistive pressure sensor has been designed, fabricated and tested in the range of 0 to 1 bar and temperature range of 20/spl deg/C to 80/spl deg/C. A suitable signal conditioning analog circuit consisting of constant current generator and an offset adjustable low noise instrumentation amplifier has been designed and tested. The analog output is then digitized through an ADC and fed to FPGA. Architecture for compensation of nonlinear temperature dependence of pressure sensor has been implemented and tested in FPGA. A device model of porous silicon pressure sensor has also been developed with a view to realize a SMART pressure sensor.

关键词： Fabrication Silicon Micromechanical devices Intelligent sensors Circuit testing Temperature sensors Field programmable gate arrays Circuit simulation Piezoresistance Temperature distribution

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A new negative-differential-resistance effect in 350 GHz SiGe HBTs operating at cryogenic temperatures

A new negative-differential-resistance effect in 350 GHz SiG...

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2005 International Semiconductor Device Research Symposium

作者： Liang, Q. Krithivasan, R. Ahmed, A. Lu, Y. Li, Y. Cressler, J.D. Niu, G. Rieh, J.-S. Freeman, G. Ahlgren, D. Joseph, A. School of Electrical and Computer Engineering Georgia Tech. Atlanta GA 30332 United States ECE Dept. Auburn University Auburn AL 36830 United States IBM Hopewell Junction NY 12533 United States IBM Essex Junction VT 05452 United States Department of Electronics and Computer Engineering Korea University Seoul Korea Republic of

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ISBN: (纸本)1424400848

No abstract available

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Fully integrated ferrite-based inductors for RF ICs

Fully integrated ferrite-based inductors for RF ICs

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International Conference on Solid State Sensors and Actuators (TRANSDUCERS)

作者： F. Liu C. Yang T.L. Ren L.T. Liu H.G. Feng A.Z. Wang H.B. Long J. Yu Institute of Microelectronics Tsinghua University China Integrated Electronics Laboratory Department of ECE Illinois Institute of Technology USA Department of Electronic Engineering Tsinghua University China Institute of Microelectronics Huazhong University of Science and Technology China

Ferrite thin-film RF integrated inductors using IC compatible processes are proposed firstly. Ferrites (Co-based, CoFe-based, MnZn-based, NiZn-based and garnet) for RF integrated inductors are investigated, and CoZrO shows the suitable high-frequency performance for RF applications. Various inductors with different kinds of ferrite thin-films have been fabricated using fully integrated processes. A typical inductor sample with CoZrO thin-film is presented. The L and Q values of the sample are 2.05 nH and 20.5 at 2 GHz, respectively. The inductance is raised by 17% and the quality factor is raised by 41%, compared with the inductor which does not include a ferrite thin-film. With the improvement of L and Q, the size of ferrite thin-film inductors can be reduced significantly.

关键词： Radio frequency Thin film inductors Magnetic materials Ferrite films Magnetic resonance Magnetic films Soft magnetic materials Permeability Radiofrequency integrated circuits Inductance

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Efficient space/time compression to reduce test data volume and testing time for IP cores

Efficient space/time compression to reduce test data volume ...

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International Conference on VLSI Design

作者： Lei Li K. Chakrabarty S. Kajihara S. Swaminathan Department Electrical & Computer Engineering Duke University Durham NC USA Department Computer Sciences & Electronics Kyushu Institute of Information Sciences Japan IBM Microelectronics Division NC USA

ISBN: (纸本)0769522645

We present 2D (space/time) compression techniques that reduce test data volume and test application time for scan testing of intellectual property (IP) cores. We start with a set of test cubes and use the well-known concept of scan chain compatibility to determine a small number c of tester channels that are needed to drive m scan chains (c /spl Lt/ m). Next, we exploit logic dependencies between the test data for the scan chains to design a single-level decompression circuit based on two-input gates. We refer to these procedures collectively as width (space) compression. We then determine a small set of test patterns that can provide complete fault coverage when they are applied to the circuit under test using the c tester channels; this procedure is referred to as height (time) compression. In this way, structural information about the IP cores is not necessary for fault simulation, dynamic compaction, or test generation. The hardware overhead of the proposed approach is limited to the fan-out structure and a very small number of gates between the tester-driven external scan pins and the internal scan chains. Results are presented for the ISCAS-89 benchmarks and for four industrial circuits.

关键词： Circuit testing Logic testing Circuit faults Intellectual property Logic design Logic circuits Circuit simulation Compaction Hardware Pins

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Advanced MOSFETs using HfTaON/SiO/sub 2/ gate dielectric and TaN metal gate with excellent performances for low standby power application

Advanced MOSFETs using HfTaON/SiO/sub 2/ gate dielectric and...

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International Electron Devices Meeting (IEDM)

作者： Xiongfei Yu Chunxiang Zhu Mingbin Yu M.F. Li A. Chin C.H. Tung D. Gui Dim-Lee Kwong SNDL Department of ECE National University of Singapore Singapore Institute of Microelectronics Singapore Department of Electronics Engineering National Chiao Tung University Taiwan Chartered Semiconductor Manufacturing Private Limited Singapore

In this work, a novel HfTaON/SiO 2 gate dielectric with metal gate has been investigated for low standby power CMOS application. This gate stack exhibits excellent electrical performances, including low leakage current relative to Hf-silicates, good thermal stability, very low interface state density, superior electron and hole mobilities (100% and 96% of universal curves at 0.8 MV/cm), and excellent BTI characteristic. Therefore, the HfTaON/SiO 2 has a potential to replace current SiO 2 and SiON as the gate dielectric for advanced low standby power application

关键词： MOSFETs Annealing Hafnium Dielectric substrates Buffer layers Temperature Leakage current Dielectric materials Degradation Dry etching

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A New Negative-Differential-Resistance Effect in 350 GHz SiGe HBTs Operating at Cryogenic Temperatures

A New Negative-Differential-Resistance Effect in 350 GHz SiG...

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International Symposium Semiconductor Device Research (ISDRS)

作者： Q. Liang R. Krithivasan A. Ahmed Y. Lu Y. Li J.D. Cressler G. Niu J.-S. Rieh G. Freeman D. Ahlgren A. Joseph School of Electrical and Computer Engineering Georgia Tech Atlanta GA USA ECE Department Aubum University Auburn AL USA Department of Electronics and Computer Engineering Korea University Seoul South Korea IBM Hopewell Junction NY USA IBM Essex Junction VT USA

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