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High-level partitioning of digital systems based on dynamically reconfigurable devices

作者： Kielbik, Rafal Moreno, Juan Manuel Napieralski, Andrzej Jablonski, Grzegorz Szymanski, Tomasz Department of Microelectronics and Computer Science Technical University of Lodz Al. Politechniki 11 93-590 Lodz Poland Department of Electronics Engineering Technical University of Catalunya c/ Gran Capita s/n 08034 Barcelona Spain

ISBN: (纸本)3540441085

This paper presents a high-level temporal partitioning algorithm, which is able to split the VHDL description of a digital system into two equivalent subdescriptions. The primary goal of the algorithm is to obtain two area-balanced, time-independent partitions. The descriptions of these partitions can be separately simulated, synthesized and implemented as different configurations of a dynamically reconfigurable device. The partitioning principle is based on a directed task hypergraph. Each vertex of this hypergraph corresponds to one concurrent assignment of the description being analysed. The resources required for the physical implementation of each vertex are calculated by means of a simplified resource estimator. Time dependencies between vertices are denoted by hyperedges representing signals connecting appropriate concurrent assignments. © Springer-Verlag Berlin Heidelberg 2002.

关键词： Digital devices

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A method of static test compaction based on don't care identification

A method of static test compaction based on don't care ident...

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IEEE International Workshop on Electronic Design, Test and Applications (DELTA)

作者： K. Miyase S. Kajihara S.M. Reddy Department of Computer Sciences and Electronics Kyushu Institute of Technology Japan Department of Computer Sciences and Electronics Center for Microelectronics Systems Kyushu Institute of Technology Japan Electrical and Computer Engineering Department University of Iowa USA

ISBN: (纸本)0769514537

In this paper, we propose a procedure to compact a test set for a combinational circuit. Given a test set in which all input values are specified, the procedure first identifies don't care inputs of the test set, and next reassigns appropriate values to the don't cares to achieve test compaction. The procedure can be applied repeatedly, until further compaction cannot be derived. Experimental results show effectiveness of the proposed procedure for the ISCAS benchmark circuits.

关键词： Compaction Circuit testing Circuit faults Fault detection Electronic equipment testing Logic testing Electrical fault detection Combinational circuits microelectronics System testing

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On test data volume reduction for multiple scan chain designs

On test data volume reduction for multiple scan chain design...

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VLSI Test Symposium

作者： S.M. Reddy K. Miyase S. Kajihara I. Pomeranz Electrical and Computer Engineering Department University of Iowa USA Department of Computer Sciences and Electronics Kyushu Institute of Technology Japan Center for Microelectronics Systems Kyushu Institute of Technology Japan School of Electrical and Computer Engineering Purdue University USA

We consider issues related to the reduction of scan test data in designs with multiple scan chains. We propose a metric that can be used to evaluate the effectiveness of procedures for reducing the scan data volume. The metric compares the achieved compression to the compression which is intrinsic to the use of multiple scan chains. We also propose a procedure for modifying a given test set so as to achieve reductions in test data volume assuming a combinational decompressor circuit.

关键词： Circuit testing Encoding Data engineering Design engineering Electronic equipment testing Very large scale integration microelectronics System testing Costs Circuit faults

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High frequency optical integrated circuit design and first iteration realisation in standard silicon CMOS integrated circuitry

High frequency optical integrated circuit design and first i...

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International Symposium on Electron Devices for Microwave and Optoelectronic Applications (EDMO)

作者： L.W. Snyman A. Bogalecki L.M. Canning M. Du Plessis H. Aharoni Currently at the Department of Electronic Engineering and the French South African Tcchnical Institute in Electronics Pretoria South Africa Carl and Emily Fuchs Institute for Microelectronics Department of Electrical Electronic and Computer Engineering University of Pretoria Pretoria South Africa Department of Electrical and Computer Engineering Carl and Emily Fuchs Institute for Microelectronics Beersheba Israel

A prototype silicon CMOS optical integrated circuit (Si CMOS OEIC) was designed and simulated using standard 0.8 /spl mu/m Bi-CMOS silicon integrated circuit technology. The circuit consisted of an integrated silicon light emitting source, an optical wave-guiding structure, two integrated optical detectors and two high-gain CMOS trans-impedance based analogue amplifiers. Simulations with MicroSim PSpice software predict a typical mean bandwidth capability of 185 MHz for the trans-impedance amplifier for detected photo-currents at the input of the amplifier in the range of 1 nA to 100 nA and driving a 10 k/spl Omega/ load. First iteration waveguiding structures were realised in 1.2 /spl mu/m CMOS technology for various source-waveguide-detector arrangements. Signal coupling ranging from 1 nA to 1 /spl mu/A was detected at the detectors. The technology seems favourable for first-iteration implementations as diverse opto-electronic applications in silicon - CMOS integrated circuitry.

关键词： Frequency Integrated optics Integrated circuit synthesis Silicon Stimulated emission Integrated circuit technology Optical amplifiers CMOS technology Circuit simulation Virtual prototyping

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Modelling and analysis of power dissipation in single electron logic

Modelling and analysis of power dissipation in single electr...

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International Electron Devices Meeting (IEDM)

作者： S. Mahapatra A.M. Ionescu K. Banerjee M.J. Declercq Electronics Laboratory (LEG) Institute of Microelectronics and Microsystems Imm. Swiss Federal Institute of Technology Lausanne Switzerland Department of Electrical and Computer Engineering University of California Santa Barbara CA USA Electronics Laboratory (LEG) Institute of Microelectronics and Microsystems Imm Swiss Federal Institute of Technology Lausanne Switzerland

A new analytical model for Single Electron Transistors (SETs) that can be used for co-simulation with CMOS is developed and validated with Monte Carlo simulation. The model includes temperature dependence, device asymmetry and background charge effects. A detailed physical parameter extraction procedure for asymmetric SETs is reported. An analytical approach is subsequently developed to investigate and accurately predict the power dissipation of SET inverters. Static power, as the main mechanism of SET logic power dissipation, and contributions of dynamic and temperature-dependent leakage power are derived and critically discussed. It is shown that SET asymmetry can be exploited to significantly reduce SET logic power dissipation with negligible impact on propagation delay.

关键词： Power dissipation Semiconductor device modeling Logic devices CMOS logic circuits Analytical models Single electron transistors Temperature dependence Parameter extraction Inverters Propagation delay

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Guest editorial special section on issues related to semiconductor manufacturing at technology nodes below 70 nm

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IEEE Transactions on Semiconductor Manufacturing 2002年第2期15卷 133-136页

作者： R. Singh R.R. Doering H. Koike Kinam Kim M. Heyns Department of Electrical and Computer Engineering Clemson University Clemson SC USA Texas Instruments Incorporated Dallas TX USA Toshiba Corporation Semiconductor Company Advanced Microelectronics Center Yokohama Japan Samsung Electronics Kyunggi-Do Korea IMEC Leuven Belgium

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Innovative nitride passivation for pseudomorphic GaAs HEMTs and impact on device performance

Innovative nitride passivation for pseudomorphic GaAs HEMTs ...

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Annual International Symposium on Reliability Physics

作者： Y.C. Chou P. Nam G.P. Li L.K. Kim R. Grundbacher E. Ahlers Y. Ra Q. Xu M.B. Biedenbender A. Oki Microelectron. Products & Processes TRW Space & Electron. Redondo Beach CA USA Department of Electrical and Computer Engineering University of California Irvine CA TRW Space and Electronics Microelectronics Products and Processes Redondo Beach CA Bethel Material Research Placentia CA

ISBN: (纸本)0780373529

A novel low temperature nitride deposition technique using high-density inductively coupled plasma chemical vapor deposition (HD-ICP-CVD) to passivate 0.15 /spl mu/m pseudomorphic GaAs HEMTs has been developed for the first time. SiH/sub 4//N/sub 2/ chemistries are used in HD-ICP-CVD for nitride deposition instead of SiH/sub 4//NH/sub 3//N/sub 2/ in plasma-enhanced CVD (PECVD). HD-ICP-CVD nitride films have a lower wet BOE etch rate and lower hydrogen concentration than those of nitride films deposited by PECVD. Nitride films with high density and low hydrogen concentration provide a potential improvement of hermeticity and reliability, which are crucial for MMIC insertion in the commercial arena. Furthermore, HD-ICP-CVD passivated devices exhibit better performance combinations of reverse breakdown voltage, transconductance, and cutoff frequency than those of PECVD passivated devices. The results achieved here warrant the application of HD-ICP-CVD for next-generation nitride passivation in compound semiconductor technologies.

关键词： Passivation Gallium arsenide HEMTs MODFETs Plasma chemistry Plasma temperature Plasma applications Hydrogen Plasma devices Chemical vapor deposition

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Raman and photoluminescence characterization of Ge nanocrystals in co-sputtered Ge + SiO2 system

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Materials Science and engineering C 2001年第1-2期16卷 135-138页

作者： Choi, W.K Ng, V. Ho, Y.W Ng, S.P Chen, T.B Yu, M.B Rusli Yoon, S.F Cheong, B.A Chen, G.L Microelectronics Laboratory Department of Electrical and Computer Engineering National University of Singapore 4 Engineering Drive 3 Singapore 117576 Singapore School of Electrical and Electronics Engineering Nanyang Technological University Nanyang Avenue Singapore 639798 Singapore Data Storage Institute 5 Engineering Drive 1 Singapore 117608 Singapore

Raman and photoluminescence (PL) results of Ge nanocrystals prepared from co-sputtered Ge + SiO2 samples under rapid-thermal annealling (RTA) with different annealing conditions are presented. The Raman results showed a transition from amorphous to nanocrystalline Ge when the samples were annealed at a temperature higher than 700 °C for longer than 300 s. The Raman spectrum of sample annealed at 1000 °C is very similar to that of the as-deposited amorphous sample. However, when the annealing duration is reduced to less than 50 s, clear Raman signals can be seen for samples annealed at 1000 °C. Transmission electron micrographs showed that uniform Ge nanocrystals were obtained for samples annealed at 800 °C for 300 s or 1000 °C for 50 s, and nanocrystals with multiple twinned structure (of diameter ~ 200 Å) were observed near the Si-SiO2 interface (1000 °C for 300 s). PL results showed that maximum intensity of the 1.9 and 3.0 eV peaks was obtained from samples annealed at 800 °C for 20 s or transiently to 1000 °C at 30 °C/s. These results suggest that a critical thermal budget is required for the formation of uniform nanocrystals and for maximum PL emission. © 2001 Elsevier Science B.V. All rights reserved.

关键词： Nanostructured materials

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An automated tool for analysis and design of MVL digital circuits

An automated tool for analysis and design of MVL digital cir...

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Symposium on Integrated Circuits and Systems Design (SBCCI)

作者： L.P. Nascimento Department of Electronics and Microelectronics School of Electrical and Computer Engineering State University of Campinas-UNICAMP Brazil

In the development of logical circuits projects in Multivalued Logic, it is necessary to obtain the result of logical expressions that sometimes are very large and complex. A software called ELOmv, that is capable of calculating the truth-table for expressions in ternary or quaternary level with even three variables of entry is presented. The non-classical algebra of MVL based on Post algebra, used in this work is shown, as well as the operators and the synthesis of the logical functions. This software is a tool that can be used in a future work in which synthesis and simplification of logical functions will be performed.

关键词： Digital circuits Algebra Multivalued logic Fuzzy logic Artificial intelligence CMOS technology microelectronics Software performance Software tools Emulation

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A system for tracking laboratory animals based on optical flow and active contours

A system for tracking laboratory animals based on optical fl...

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International Conference on Image Analysis and Processing

作者： Z. Kalafatic S. Ribaric V. Stanisavljevic Faculty of Electrical Engineering and Computing Department of Electronics Microelectronics Computer and Intelligent Systems Zagreb Croatia

We present a working system for real-time tracking of multiple laboratory animals. As it is usually possible to ensure good contrast between the animals and the background, the tracking of a single animal or several physically separated animals can be obtained by relatively simple algorithms. The main problem arises when we try to track several almost identical, uniformly coloured animals during their contacts. To deal with this problem, we utilize dynamic information extracted by estimating sparse optical flow along the object contours. Optical flow vectors are used for updating the positions of the tracked contours in a sequence of image frames. The local properties of optical flow enable the system to track the objects during their contact, although some parts of the object contours become hidden. The missing dynamic information is reconstructed by using a model of constant optical flow along an object contour. The reconstructed contours are then adjusted to real object boundaries in the current frame by using an active contour model. The robustness of the tracking algorithm is improved by adding a supervision module, which detects tracking failures and reinitialises the contours that lose their targets. The system has been tested on real sequences with laboratory animals during pharmacological experiments and has been shown to be robust and efficient. Future extensions will include expert knowledge of biomedical and pharmacological experts. The major goal is to build a system that will provide an objective and standardised tool for evaluation of animal behaviour during experiments.

关键词： Laboratories Animals Image motion analysis Biomedical optical imaging Image reconstruction Robustness Target tracking Real time systems Data mining Active contours

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