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International Symposium on Information Processing in Sensor Networks (IPSN)

作者： Heemin Park Jeff Burke Mani B. Srivastava System LSI Division Samsung Electronics Camera Processor Design Yongin si South Korea REMAP UCLA Los Angeles CA USA NESL/EE Department UCLA Los Angeles CA USA

We present the design and implementation of the Illuminator, a preliminary sensor network-based intelligent light control system for entertainment and media production. Unlike most sensor network applications, which focus on sensing alone, a distinctive aspect of Illuminator is that it closes the loop from light sensing to lighting control. We describe the Illuminator's design requirements, system architecture, algorithms, implementation and experimental results. To satisfy the high-performance light sensing requirements of entertainment and media production applications, the system uses the Illumimote, which is a multi-modal and high fidelity light sensor module well-suited to wireless sensor networks. The Illuminator system is a toolset to characterize the illumination profile of a deployed set of fixed position lights, generate desired lighting effects for moving targets (actors, scenic elements, etc.) based on user constraints expressed in a formal language, and assist in the set up of lights to achieve the same illumination profile in multiple venues. After characterizing deployed lights, the Illuminator computes at run-time optimal light settings to achieve a user-specified actuation profile using an optimization framework based on a genetic algorithm Uniquely, it can use deployed sensors to incorporate changing ambient lighting conditions and moving targets into actuation. With experimental results, we demonstrate that the Illuminator handles various high-level user's constraints and generates optimal light actuation profile. These results suggest that our system should support entertainment and media production applications.

关键词： Wireless sensor networks Intelligent control Intelligent networks Intelligent sensors Lighting control Production systems Sensor phenomena and characterization Sensor systems Intelligent systems Control systems

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A novel nonvolatile memory with spin torque transfer magnetization switching: spin-ram

A novel nonvolatile memory with spin torque transfer magneti...

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International Electron Devices Meeting (IEDM)

作者： M. Hosomi H. Yamagishi T. Yamamoto K. Bessho Y. Higo K. Yamane H. Yamada M. Shoji H. Hachino C. Fukumoto H. Nagao H. Kano Solid State Memories Research Laboratory Information Technologies Laboratories Sony Corporation Atsugi Kanagawa Japan Semiconductor Technology Development Group Semiconductor Solution Network Company Sony Corporation Atsugi Kanagawa Japan Semiconductor Technology Development Group Semiconductor Solution Network Company Sony Corporation Memory Design Section 3 LSI Library Design DepartmentSystem LSI Products Division 1 Sony Semiconductor Kyushu Corporation Atsugi Kanagawa Japan

A novel nonvolatile memory utilizing spin torque transfer magnetization switching (STS), abbreviated spin-RAM hereafter, is presented for the first time. The spin-RAM is programmed by magnetization reversal through an interaction of a spin momentum-torque-transferred current and a magnetic moment of memory layers in magnetic tunnel junctions (MTJs), and therefore an external magnetic field is unnecessary as that for a conventional MRAM. This new programming mode has been accomplished owing to our tailored MTJ, which has an oval shape of 100 times 150 nm. The memory cell is based on a 1-transistor and a 1-MTJ (ITU) structure. The 4kbit spin-RAM was fabricated on a 4 level metal, 0.18 mum CMOS process. In this work, writing speed as high as 2 ns, and a write current as low as 200 muA were successfully demonstrated. It has been proved that spin-RAM possesses outstanding characteristics such as high speed, low power and high scalability for the next generation universal memory

关键词： Nonvolatile memory Torque Magnetic switching Magnetic tunneling Sociotechnical systems Magnetization reversal Magnetic moments Magnetic fields Shape CMOS process

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Low-power design methodology and applications utilizing dual supply voltages 00

Low-power design methodology and applications utilizing dual...

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2000 Asia and South Pacific design Automation Conference, ASP-DAC 2000

作者： Usami, Kimiyoshi Igarashi, Mutsunori Design Methodology Department System LSI Design Division Toshiba Corporation 580-1 Horikawa-cho Saiwai-ku Kawasaki 210-8520 Japan

ISBN: (纸本)0780359747

This paper describes a gate-level power minimization methodology using dual supply voltages. Gates and flip-flops off the critical paths are made to operate at the reduced supply voltage to save power. Core technologies are dual-V DD circuit synthesis and P&R. We give a brief overview on existing low-power EDA technologies as background and discuss advantages and challenges of the dual-VDD approach. Through real design examples, we will show that the approach reduces power effectively while keeping the performance at negligible area overhead. © 2000 IEEE.

关键词： Flip flop circuits

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Repeater insertion method and its application to a 300 MHz 128-bit 2-way superscalar microprocessor

Repeater insertion method and its application to a 300 MHz 1...

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Asia and South Pacific design Automation Conference

作者： N. Kojima Y. Paramwswar C. Klingner Y. Ohtaguro M. Matsui S. Iwasa T. Teruyama T. Shimazawa H. Takeda K. Hashizume H. Tago M. Yamada Design Methodology Department System LSI Design Div Toshiba Corporation Semiconductor Company Kawasaki Japan Toshiba America Electrical Components Inc. San Jose CA USA System ULSI Engineering Laboratory Toshiba Corporation Semiconductor Company Kawasaki Japan RISC Processor Development Department Microprocessor Div Toshiba Corporation Semiconductor Company Kawasaki Japan Microprocessor Design Department System LSI Design Division Toshiba Corporation Semiconductor Company Kawasaki Japan Advanced LSI Technology Development Department Toshiba Microelectronics Corporation Kawasaki Japan

Interconnect delay is dominant in today's high speed Vlsi circuits and there have been various studies on ways to resolve it. A repeater insertion tool "RePertory" has been developed to solve the interconnect timing problem on a 300 MHz 128-bit 2-way superscalar microprocessor. Because of its practical simple algorithm, the location of over 5700 repeaters distributed over 5 modules is calculated in 26 minutes on 5 UltraSPARC-II 360 MHz in parallel. This paper describes the goals of RePertory for this project, the timing improvement flow with RePertory, the results and analysis of this repeater insertion method.

关键词： Repeaters microprocessors Timing Large scale integration Integrated circuit interconnections Delay Very large scale integration Electromigration Engines Automatic control

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Find all solutions of piecewise-linear resistive circuits using an LP test

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IEEE Transactions on Circuits and systems I: Fundamental Theory and Applications 2000年第7期47卷 1115-1120页

作者： K. Yamamura K. Yomogita Department of Electrical ElectronicCommunication EngineeringFaculty of Science and Engineering Chuo University Tokyo Japan Design System Department LSI Division OKI Electric Industry Company Limited Tokyo Japan

An efficient algorithm is proposed for finding all solutions of piecewise-linear (PWL) resistive circuits using linear programming (LP). This algorithm is based on a simple test (termed the LP test) for nonexistence of a solution to a system of PWL equations in a given region. In the LP test, the system of PWL equations is transformed into an LP problem, to which the simplex method is applied. Such an LP problem is obtained by surrounding the PWL functions by rectangles. It is shown that the LP test can deal with nonseparable functions of more than one variable by using more than two-dimensional rectangles. It is also shown that, for bipolar transistor circuits, the LP test becomes more efficient and more powerful by surrounding the exponential functions by right-angled triangles. The proposed algorithm is simple, efficient, and can be easily implemented.

关键词： Circuit testing Piecewise linear techniques Linear programming system testing Nonlinear equations Computational efficiency Bipolar transistor circuits Computational complexity Performance evaluation Large scale integration

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A low-power cache system for embedded processors

A low-power cache system for embedded processors

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Midwest Symposium on Circuits and systems (MWSCAS)

作者： Gi-Ho Park Kil-Whan Lee Jang-Soo Lee Tack-Don Han Shin-Dug Kim Yong-Chun Kim Seh-Woong Jeong Kwang-Yup Lee Research Institute of ASIC Design Yonsei University Seoul South Korea Department of Computer Science Yonsei University Seoul South Korea MCU Team System LSI Division Samsung Electronics Company Limited Yongin si South Korea Department of Computer Engineering Seokyeong University Seoul South Korea

A low-power cache structure for embedded processors, called a cooperative cache system, is presented in this paper. The cooperative cache system reduces power consumption of the cache system by virtue of the structural characteristics that consists of two separate caches having different associativities and block sizes. The cooperative cache system is adopted as the cache structure for the CalmRISC-32 embedded processor, the prototype chip of which was recently manufactured with a 0.25 /spl mu/m, 4-metal process by Samsung Electronics Co.

关键词： Cooperative caching Energy consumption Application specific integrated circuits Computer science Large scale integration Embedded computing Power engineering computing design engineering Power engineering and energy Manufacturing processes

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Intermodulation analysis of mixer circuits based on frequency domain relaxation method

Intermodulation analysis of mixer circuits based on frequenc...

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Custom Integrated Circuits Conference (CICC)

作者： A. Ushida Y. Yamagami Y. Nishio M. Takahashi K. Ogawa Department of Electrical and Electronic Engineering University of Tokushima Tokushima Japan Custom DA Section Design Automation Department LSI System Development Division SONY Company Limited Atsugi Kanagawa Japan

There are many communication circuits driven by multi-tone signals such as modulators and mixers. If the output frequency components are largely different to each other, the brute force numerical method will take an enormous computation time to calculate the steady-state responses, because the total period becomes very long. In this paper, we show a SPICE oriented algorithm based on the frequency domain relaxation method which can be efficiently applied to relatively large scale ICs.

关键词： Circuit analysis Frequency domain analysis Relaxation methods Steady-state SPICE Large-scale systems Nonlinear circuits design engineering design automation Large scale integration

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A study of fully silicided 0.18 /spl mu/m CMOS ESD protection devices

A study of fully silicided 0.18 /spl mu/m CMOS ESD protectio...

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Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)

作者： T. Suzuki S. Mitarai S. Ito H. Monma N. Higashi Advanced CMOS Technology Department LSI Group Fujitsu Laboratories Limited Kuwana-gun Mie Japan Manufacturing Engineering Division LSI Group Fujitsu Laboratories Limited Kuwana-gun Mie Japan System LSI Design Dep Fujitsu VLSI Limited Kuwana-gun Mie Japan

We studied the optimization of an ESD protection circuit based on MM and HBM test results using a test element group (TEG) created in a fully silicided 0.1 /spl mu/m CMOS process. We concluded that the change in drain area and channel width had different effects on the ESD robustness of different test items because the type of operating ESD protection element was determined by the polarity of the ESD surge applied. In addition, we found that, due to the formation of silicides in a source and drain contact, the dimensions around the contact had less influence on ESD robustness, while the channel width had a large influence on ESD robustness.

关键词： Electrostatic discharge Protection Large scale integration CMOS technology Circuit testing Robustness Semiconductor devices Packaging CMOS process Silicides

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PASTEL: A parameterized memory characterization system

PASTEL: A parameterized memory characterization system

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design, Automation and Test in Europe Conference (DATE98)

作者： Ogawa, K Kohno, M Kitamura, F Design Automation Department System LSI Division Semiconductor Company Sony Japan

ISBN: (纸本)0818683597

PASTEL is a parameterized memory characterization system which extracts the characteristics of ASIC on-chip-memories such as delay, timing and power consumption which are important in lsi logic design. PASTEL is a fully-automated process from exact wire-RC extraction through circuit reduction, input vector generation, waveform measurement, data-sheet and library creation. The circuit reduction scheme can reduce the circuit simulation time by 2 order of magnitude while maintaining delay error within 100pSec of exact simulation.

关键词： Delay circuits

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PASTEL: a parameterized memory characterization system 98

PASTEL: a parameterized memory characterization system

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design, Automation and Test in Europe Conference and Exhibition

作者： K. Ogawa M. Kohno F. Kitamura Design Automation Department System LSI Division Semiconductor Company Japan

ISBN: (纸本)9780818683596

关键词： Data mining Circuit simulation Character generation

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