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Conference on Open Architecture Control Systems and Standards

作者： Gower, A Boning, D McIlrath, M Microsystems Technology Laboratories Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology Cambridge MA 02139 United States

ISBN: (纸本)0819423149

Semiconductor fabrication requires an increasingly expensive and integrated set of tightly controlled processes, driving the need for a fabrication facility with fully computerized, networked processing equipment. We describe an integrated, open system architecture enabling distributed experimentation and process control for plasma etching. The system was developed at MIT's microsystems technology laboratories and employs in-situ CCD interferometry based analysis in the sensor-feedback control of an Applied Materials Precision 5000 Plasma Etcher (AME5000). Our system supports accelerated, advanced research involving feedback control algorithms, and includes a distributed interface that utilizes the internet to make these fabrication capabilities available to remote users. The system architecture is both distributed and modular: specific implementation of any one task does not restrict the implementation of another. The low level architectural components include a host controller that communicates with the AME5000 equipment via SECS-II, and a host controller for the acquisition and analysis of the CCD sensor images. A Cell Controller (CC) manages communications between these equipment and sensor controllers. The CC is also responsible for process control decisions;algorithmic controllers may be integrated locally or via remote communications. Finally, a System Server manages connections from internet/intranet (web) based clients and uses a direct link with the CC to access the system. Each component communicates via a predefined set of TCP/IP socket based messages. This flexible architecture makes integration easier and more robust, and enables separate software components to run on the same or different computers independent of hardware or software platform.

关键词： distributed architecture in-situ data acquisition semiconductor process control distributed interface

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Architecture for distributed design and fabrication

Architecture for distributed design and fabrication

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Plug and Play Software for Agile Manufacturing

作者： McIlrath, Michael B. Boning, Duane S. Troxel, Donald E. Massachusetts Institute of Technology Microsystems Technology Laboratories Department of Electrical Engineering and Computer Science Cambridge MA 02139 United States

We describe a flexible, distributed system architecture capable of supporting collaborative design and fabrication of semi-conductor devices and integrated circuits. Such capabilities are of particular importance in the development of new technologies, where both equipment and expertise are limited. Distributed fabrication enables direct, remote, physical experimentation in the development of leading edge technology, where the necessary manufacturing resources are new, expensive, and scarce. Computational resources, software, processing equipment, and people may all be widely distributed;their effective integration is essential in order to achieve the realization of new technologies for specific product requirements. Our architecture leverages is essential in order to achieve the realization of new technologies for specific product requirements. Our architecture leverages current vendor and consortia developments to define software interfaces and infrastructure based on existing and merging networking, CIM, and CAD standards. Process engineers and product designers access processing and simulation results through a common interface and collaborate across the distributed manufacturing environment. ©2005 Copyright SPIE - The International Society for Optical engineering.

关键词： Fabrication

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Determination of the band offset of GaInP-GaAs and AlInP-GaAs quantum wells by optical spectroscopy

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JOURNAL OF ELECTRONIC MATERIALS 1997年第8期26卷 944-948页

作者： Kuo, HC Kuo, JM Wang, YC Lin, CH Chen, H Stillman, GE Department of Electrical and Computer Engineering Microelectronics Laboratory Center for Compound Semiconductor Microelectronics University of Illinois at Urbana-Champaign Urbana Lucent Technology Bell Laboratories Murray Hill Department of Material Science and Engineering Material Research Laboratory University of Illinois at Urbana-Champaign Urbana

We report the determination of band offset ratios, using photoluminescence excitation measurements, for GaInP/GaAs and AIInP/GaAs quantum wells grown by gas-source molecular beam epitaxy. To reduce the uncertainty related to the intermixing layer at heterointerfaces, the residual group-V source evacuation time was optimized for abrupt GaInP/GaAs (AIInP/GaAs) interfaces. Based upon thickness and composition values determined by double-crystal x-ray diffraction simulation and cross-sectional transmission electron microscopy, the transition energies of GaInP/GaAs and AIInP/GaAs quantum wells were calculated using a three-band Kane model with varying hand-offset ratios The best fit of measured data to calculated transition energies suggests that the valence-band offset ratio (Gamma band discontinuity) was 0.63 +/- 0.05 for GaInP-GaAs and 0.54 +/- 0.05 for AIInP/GaAs heterostructures, This result showed good agreement with photoluminescence data, indicating that the value is dependent of temperature.

关键词： AlInP/GaAs band offset GaInP/GaAs gas source molecular beam epitaxy (GSMBE) photoluminescence (PL) photoluminescence excitation (PLE) three-band Kane

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Measurement of band offsets in Si/Si1-xGex and Si/Si1-x-yGexCy heterojunctions

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Journal of Vacuum science & technology B: Microelectronics Processing and Phenomena 1997年第4期15卷 1108-1108页

作者： Stein, B.L. Yu, E.T. Croke, E.T. Hunter, A.T. Laursen, T. Bair, A.E. Mayer, J.W. Ahn, C.C. Department of Electrical and Computer Engineering University of California San Diego La Jolla California 92093-0407 Hughes Research Laboratories Malibu California 90265 Center for Solid State Science Arizona State University Tempe Arizona 85287-1704 California Institute of Technology Pasadena California 91125

Realization of group IV heterostructure devices requires the accurate measurement of the energy band offsets in Si/Si1−xGex and Si/Si1−x−yGexCy heterojunctions. Using admittance spectroscopy, we have measured valence-band offsets in Si/Si1−xGex heterostructures and conduction-band and valence-band offsets in Si/Si1−x−yGexCy heterostructures grown by solid-source molecular-beam epitaxy. Measured Si/Si1−xGex valence-band offsets were in excellent agreement with previously reported values. For Si/Si1−x−yGexCy our measurements yielded a conduction-band offset of 100±11 meV for a n-type Si/Si0.82Ge0.169C0.011 heterojunction and valence-band offsets of 118±12 meV for a p-type Si/Si0.79Ge0.206C0.004 heterojunction and 223±20 meV for a p-type Si/Si0.595Ge0.394C0.011 heterojunction. Comparison of our measured band offsets with previously reported measurements of energy band gaps in Si1−x−yGexCy and Si1−yCy alloy layers indicates that the band alignment is type I for the compositions we have studied and that our measured band offsets are in quantitative agreement with these previously reported results.

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Epitaxy-on-electronics enhancement of GaAs IC performance with monolithic optical and quantum-effect devices

Epitaxy-on-electronics enhancement of GaAs IC performance wi...

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Advanced Workshop on Frontiers in Electronics, WOFE

作者： C.G. Fonstad J.F. Ahadian S.G. Patterson P.T. Vaidyanathan Y. Royter G. Petrich L.A. Kolodziejski S. Prasad National Center for Integrated Photonics Technology (NCIPT) Research Laboratory of Electronics (RLE) Microsystems Technology Laboratory and Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology Cambridge MA USA

An integration technique, epitaxy-on-electronics (EoE), is described wherein optoelectronic and quantum effect device heterostructures are grown on fully processed GaAs integrated circuit chips and subsequently processed into devices monolithically integrated with the pre-existing circuitry. Using this technique, one can realize the increased performance and functionality promised by adding advanced heterostructure quantum effect and optoelectronic devices to conventional integrated electronic circuitry, without developing a complete new VLSI technology. The details of the EoE technology are explained, and examples of optoelectronic integrated circuits incorporating LEDs, detectors, and MESFET electronics are presented. The OPTOCHIP Project, a prototype EoE research OEIC foundry, and work on EoE integration of resonant tunneling diodes to form one-transistor GaAs static random access memory cells, are also described.

关键词： Gallium arsenide Optoelectronic devices Integrated circuit technology MESFET integrated circuits Monolithic integrated circuits Very large scale integration Light emitting diodes Detectors Prototypes Foundries

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Generating reduced order models via PEEC for capturing skin and proximity effects

Generating reduced order models via PEEC for capturing skin ...

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IEEE Topical Meeting on electrical Performance of Electronic Packaging (EPEPS)

作者： M. Kamon N. Marques L.M. Silveira J. White Research Laboratory of Electronics Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology Cambridge MA USA INESC/Cadence European Laboratories. Department of Electrical and Computer Engineering Instituto Superior Tecnico Lisboa Portugal

In the past, model order reduction techniques have been successfully employed for 3-D PEEC (Partial Element Equivalent Circuit) interconnect models. This paper explores the difficulties in generating low order models ... 详细信息

关键词： Skin Integrated circuit interconnections Conductors Proximity effect Computational modeling Circuit simulation Equivalent circuits Admittance Voltage Jacobian matrices

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Strontium Bismuth Tantalate Based Ferroelectric Gate Field Effect Transistor with Yttrium Oxide as the Buffer Layer

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MRS Online Proceedings Library 1997年第1期493卷 465-470页

作者： Myoung-Ho Lim T. S. Kalkur Yong-Tae Kim Department of Electrical and Computer Engineering Microelectronics Research Laboratories Colorado Springs USA Symetrix Corporation Colorado Springs USA Semiconductor Materials Laboratory Korea Institute of Science and Technology Cheongyang Seoul

We report the first demonstration of an enhancement mode n-channel metal -ferroelectric-semiconductor field effect transistor (MFISFET) realized directly on silicon with yttrium oxide as the buffer layer. The capacitance-voltage (C-V) characteristics of Metal Ferroelectric Insulator Silicon (MFIS) structures show hysteresis and the direction of hysteresis corresponds to ferroelectric polarization. The memory window in the C-V characteristics was 2V for an applied voltage of ± 10V. The memory window did not show significant change due to decrease in rate of change of sweep voltage and temperature. The transmission electron microscopy (TEM) analysis confirms the formation of an amorphous oxide layer between silicon and yttrium oxide buffer layer.

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Multi-path routing combined with resource reservation

Multi-path routing combined with resource reservation

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IEEE Annual Joint Conference: INFOCOM, IEEE computer and Communications Societies

作者： I. Cidon R. Rom Y. Shavitt Department of Electrical Engineering Technion-Israel Institute of Technology Haifa Israel Sun Microsystems Inc. Mountain View CA USA Department of Computer Science Johns Hopkins University Baltimore MD USA

In high-speed networks it is desirable to interleave routing and resource (such as bandwidth) reservation. The PNNI standard for private ATM networks is an example of an algorithm that does this using a sequential crank-back mechanism. We suggest the implementation of resource reservation along several routes in parallel. We present an analytical model that demonstrates that when there are several routes to the destination it pays to attempt reservation along more than a single route. Following this analytic observation, we present a family of algorithms that route and reserve resources along parallel subroutes. The algorithms of the family represent different trade-offs between the speed and the quality of the established route. The presented algorithms are simulated against several legacy algorithms, including the PNNI crank-back, and exhibit higher network utilization and faster connection set-up time.

关键词： Routing Sun Electronic mail High-speed networks Bandwidth B-ISDN Availability Read only memory computer science Analytical models

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Synchronous load balancing in hypercube multicomputers with faulty nodes

Synchronous load balancing in hypercube multicomputers with ...

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International Conference on Parallel and Distributed Systems (ICPADS)

作者： Jaewon Seo Sunggu Lee Jong Kim Department of Electrical Engineering Information Research Laboratories PIRL Pohang University of Science and Technology Pohang South Korea IBM Thomas J. Watson Research Center Yorktown Heights NY USA Department of Computer Science & Engineering Information Research Laboratories PIRL Pohang University of Science and Technology Pohang South Korea

ISBN: (纸本)0818682272

This paper presents a new dynamic load balancing algorithm for hypercube multicomputers with faulty nodes. The emphasis in our method is on obtaining global load information and performing task migration using "short paths" in a synchronous manner so that a minimal amount of communication overhead is required. To accomplish this, we present an algorithm for constructing a new logical topology from a hypercube topology with faulty nodes. This new topology is used to obtain the global load information and to perform task migration. Simulation results are used to evaluate the performance of our dynamic load balancing method. The proposed strategy shows good performance in the case of a small number of faulty nodes when compared with previous methods.

关键词： Load management Hypercubes Topology Concurrent computing Distributed computing Application software Heuristic algorithms Parallel processing computer networks Multiprocessor interconnection networks

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High nonlinearity, low loss fiber for 1 pJ switching of 8-ps optical pulses

High nonlinearity, low loss fiber for 1 pJ switching of 8-ps...

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Optical Fiber Communication (OFC) Conference

作者： D.A. Pastel A.F. Evans R.M. Hawk D.A. Nolan D.L. Weidman P. Dasika M. Jiang M.N. Islam D.G. Moodie Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI USA Science and Technology Division Corning Inc.orporated Corning NY USA Corning Inc Corning NY US Martlesham Heath BT Laboratories Ipswich UK

The nonlinear optical loop mirror (NOLM) configuration is shown. It consists of a central 50/50 achromatic fiber coupler for data input/output, two WDM Mach-Zehnder fiber couplers for add/drop of the control pulses an... 详细信息

ISBN: (纸本)1557524815

关键词： Optical fiber losses Optical pulses Optical fiber couplers Optical fibers Pulse measurements Optical fiber polarization Optical attenuators Fiber nonlinear optics Optical solitons Mirrors

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