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Fabrication of Polycrystalline Si 1−x Ge x Films on Oxide for Thin-Film Transistors

MRS Online Proceedings Library 1994年第1期343卷 679-684页

作者： Julie A. Tsai Andrew J. Tang Rafael Reif Department of Materials Science and Engineering Massachusetts Institute of Technology Cambridge USA Department of Electrical Engineering and Computer Science Microsystems Technology Laboratories Massachusetts Institute of Technology Cambridge USA

Polycrystalline-Si1−xGex films have been formed by various methods on oxide-coated Si substrates at temperatures ≤600°C. Compared to thermal growth, plasma deposition of poly-Si1−xGex promotes smoother films with smaller grains having a 200-dominated texture. Poly-Si1−xGex Alms formed by plasma deposition of amorphous-Si1-xGex followed by a crystallization anneal have an even smoother surface with grain sizes enhanced by an order of magnitude and a weak 111 grain texture. Hydrogen incorporated in amorphous-Si1−xGex evolves completely during crystallization without disrupting the smooth surface morphology. The largest grain sizes (∶1.3μm) are achieved in poly-Si1−xGex films formed by Si+ ion implantation for amorphization with a subsequent recrystallization anneal.

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High-frequency AC hot-carrier degradation in CMOS circuits

High-frequency AC hot-carrier degradation in CMOS circuits

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International Electron Devices Meeting (IEDM)

作者： Vei-Han Chan T.E. Kopley P. Marcoux J.E. Chung Department of Electrical Engineering and Computer Science Microsystems Technology Laboratories Massachusetts Institute of Technology Cambridge MA USA ICBD Technology Development Center Hewlett Packard Company Palo Alto CA USA

The device degradation due to hot carriers generated under high-frequency circuit operation is studied in detail. Two new degradation phenomena are observed at these high frequencies. First, voltage overshoot, due to internal MOSFET parasitic capacitances, causes enhanced hot-carrier degradation. Second, the quasi-static approximation is found to be invalid at high frequencies. For NMOSFETs, fast voltage transitions are found to induce different degradation dynamics; for PMOSFETs, donor-type interface-state generation and electron detrapping both become significant.< >

关键词： Hot carriers Degradation Circuit testing MOSFETs Voltage Stress MOS devices Frequency CMOS technology Logic testing

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Learning Qualitative Models from Physiological Signals

Learning Qualitative Models from Physiological Signals

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1994 AAAI Spring Symposium

作者： Hau, David T. Coiera, Enrico W. Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology CambridgeMA02139 United States Hewlett-Packard Laboratories Filton Road Stoke Gifford BristolBS12 6QZ United Kingdom

Physiological models represent a useful form of knowledge, but are both difficult and time consuming to generate by hand. Further, most physiological systems are incompletely understood. This paper addresses these two issues with a system that learns qualitative models from physiological signals. The qualitative representation of models allows incomplete knowledge to be encapsulated, and is based on Kuipers' approach used in his QSIM algorithm. The learning algorithm allows automatic generation of such models, and is based on Coiera's GENMODEL algorithm. We describe experiments using the learning system on data segments obtained from six patients during cardiac bypass surgery. Useful model constraints were obtained, representing both general physiological knowledge and knowledge particular to the patient being monitored. The effects of varying parameters for front-end signal processing, and varying fault tolerance levels for the subsequent learning by GENMODEL are also discussed. © 1994 AI Access Foundation. All rights reserved.

关键词： Physiological models

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Wavelength dependence of exposure window and resist profile in x‐ray lithography

Journal of Vacuum Science & Technology B: Microelectronics a...

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Journal of Vacuum science & technology B: Microelectronics and Nanometer Structures Processing, Measurement, and Phenomena 1994年第6期12卷 4044-4050页

作者： Jerry Z. Y. Guo George K. Celler Juan R. Maldonado Scott D. Hector AT&T Bell Laboratories Murray Hill New Jersey 07974 IBM Microelectronics Hopewell Junction New York 12533 Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology Cambridge Massachusetts 02139

In proximity x‐ray lithography, wavelengths in the range of 4–20 Å are used. The choice of wavelength is a complicated system issue, which depends on many lithographic aspects. Shorter wavelength x rays offer aerial image diffraction advantages. However, they may also give rise to spurious photoelectron effects. Longer wavelength x rays make mask patterning easier since the absorber can have a smaller aspect ratio for the required contrast, but a thinner, less robust membrane is needed to give the same x‐ray transmission. Softer x rays are also better absorbed in resist, reducing the exposure time, but higher absorption can have an adverse effect on the resist sidewall profile. A study is conducted to address the wavelength issue in x‐ray lithography using the exposure window, resist profiles, power efficiency, and the mask contrast as merit/cost functions. Results show that a compromise among these factors is needed to achieve best performance.

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Visible to near-infrared emission from a porous silicon device

Visible to near-infrared emission from a porous silicon devi...

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IEEE Photonics Conference (IPC)

作者： J. Penczek I-Wen Chao R.L. Smith A. Knoesen J.E. Davis H.W.H. Lee Department of Electrical and Computer Engineering University of California Davis CA USA Integrated Device Technology (IDT) Salinas CA USA Lawrence Livermore National Laboratories Livermore CA USA Department of Applied Science University of California Davis CA USA

Visible to near-infrared light emission is produced from a porous silicon device under current injection. The visible component appears bright red-orange, and is clearly observed even with room light. The room temperature photoluminescence (PL) spectrum of the porous silicon layer peaks in the red, whereas the electroluminescence (EL) spectrum is extremely broad and peaks in the near-infrared. This structure also exhibits a region of negative differential resistance. The porous silicon emitter is fabricated by initially diffusing phosphorous into a 9 /spl Omega/-cm p-type silicon wafer, creating 50 /spl mu/m wide by 2.5 mm long n+/p junctions.

关键词： Silicon devices Temperature Etching Hot carriers Voltage Chaos laboratories Photoluminescence Electroluminescence Aluminum

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Growth and Characterization of Silicon-Germanium Films on Oxide by VLPCVD/PE-VLPCVD

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MRS Online Proceedings Library 1993年第1期317卷 603-608页

作者： Tsai, Julie A. Reif, Rafael Department of Materials Science and Engineering Microsystems Technology Laboratories Massachusetts Institute of Technology Cambridge USA Department of Electrical Engineering and Computer Science Microsystems Technology Laboratories Massachusetts Institute of Technology Cambridge USA

Results of Si1−xGex deposition on oxide-coated Si substrates using a PE-VLPCVD (Plasma-Enhanced Very-Low-Pressure Chemical Vapor Deposition) reactor are presented. Thin layers of poly-Si1−xGex deposited with SiH4 and GeH4 at ≤ 600°C had low C and O levels. Two growth modes were examined at 500°C: plasma-initiated thermal growth (VLPCVD) and full plasma-enhanced deposition (PE-VLPCVD). In both cases, Ge incorporation increases sublinearly with gas ratio, growth rates increase with Ge content, and the transition temperature between polycrystalline and amorphous deposition is lower for Si1−xGex than Si. On the other hand, compared to thermal growth, plasma-enhanced deposition promotes not only higher growth rates but also improved structural properties such as smoother surface morphology, more columnar and oriented grains, and the unique feature of direct deposition onto oxide.

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Two-stage hot-carrier degradation and its impact on submicron LDD NMOSFET lifetime prediction

Two-stage hot-carrier degradation and its impact on submicro...

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International Electron Devices Meeting (IEDM)

作者： Vei-Han Chan J.E. Chung Microsystems Technology Laboratories Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology Cambridge MA USA

The device degradation of oxide-spacer LDD NMOS transistors due to hot carriers is studied in detail. It is found that the observed saturation in the degradation time dependence is due to a combination of an increase in the series resistance in the lightly-doped drain region, and a reduction of the carrier mobility in the channel and subdiffusion regions. Because the increase in series resistance eventually saturates, an asymptotic degradation rate coefficient can be used to extract a more accurate and consistent value of LDD NMOS lifetime.< >

关键词： Hot carriers Degradation MOSFET circuits MOS devices Stress Charge pumps Interface states electrical resistance measurement Voltage measurement Electric resistance

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Parameter extraction guidelines for hot-electron reliability simulation

Parameter extraction guidelines for hot-electron reliability...

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Annual International Symposium on Reliability Physics

作者： V.-H. Chan J.S. Kim J.E. Chung Deparment of Electrical Engineering and Computer Science Microsystems Technology Laboratories Massachusetts Institute of Technology Cambridge MA USA

Detailed NMOSFET parameter extraction guidelines for the hot-electron degradation models used in many circuit-level reliability simulation tools are proposed. Accurate calibration of these models to a particular technology is shown to require accounting for the asymptotic and variable power-law time dependence of hot-electron degradation, and the impact of the local oxide electric field on the critical energy for interface damage. In addition, statistical analysis is used to determine the prediction intervals within which hot-electron lifetime can be estimated, and to offer insight into developing more efficient and precise testing methodologies.< >

关键词： Parameter extraction Guidelines Degradation MOSFET circuits Circuit simulation Calibration Statistical analysis Life estimation Lifetime estimation Life testing

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A relaxation/multipole-accelerated scheme for self-consistent electromechanical analysis of complex 3-D microelectromechanical structures 93

A relaxation/multipole-accelerated scheme for self-consisten...

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IEEE International Conference on computer-Aided Design

作者： X. Cai H. Yie P. Osterberg J. Gilbert S. Senturia J. White Department of Electrical Engineering and Computer Science Research Laboratory of Electrical and Microsystems Technology Laboratory Research Laboratory of Electrical and Microsystems Technology Laboratory Cambridge MA USA

ISBN: (纸本)9780818644900

In this paper, two approaches to self-consistent electromechanical analysis of three-dimensional micro-electro-mechanical structures are described. Both approaches combine finite-element mechanical analysis with multipole-accelerated electrostatic analysis, the first using a relaxation algorithm and the second using a surface/Newton generalized conjugate-residual scheme. Examples are given to demonstrate the relative merits of the two approaches.

关键词： Electrostatic analysis Performance analysis Contracts Finite element methods Equations Stress Algorithm design and analysis Microactuators Force control Shape

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The impact of hot-electron degradation on CMOS analog subcircuit performance

The impact of hot-electron degradation on CMOS analog subcir...

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Custom Integrated Circuits Conference (CICC)

作者： Vei-Han Chan B.W. Scharf J.E. Chung Department of Electrical Engineering and Computer Science Microsystems Technology Laboratories Massachusetts Institute of Technology Cambridge MA USA Analog Devices Inc.orporated Wilmington MA USA

Experimental data on CMOS analog circuit degradation due to hot-electron effects are presented. Because of circuit design constraints, most MOSFETs used for analog applications are biased in the saturation region with low gate voltage. Under such operating conditions, in addition to interface states, significant numbers of hole traps are also generated inside NMOSFETs. Because acceptor-type interface states are mostly unoccupied in the saturation region, hole traps are found to have a much more significant impact on NMOSFET performance. It is demonstrated that analog subcircuit performance degradation is quite sensitive to the particular circuit design and operating conditions. Circuit performance and reliability tradeoffs are also evaluated.

关键词： Degradation Analog circuits Interface states Voltage Stress MOSFETs CMOS analog integrated circuits Circuit synthesis Circuit optimization Digital circuits

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