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IEEE International Conference on Micro Electro Mechanical Systems

作者： M.G. Allen M. Scheidl R.L. Smith Microsystems Technology Laboratories Massachusetts Institute of Technology Cambridge MA USA Department of Electrical Engineering and Computer Science University of California Davis Davis CA USA

A process for fabricating silicon plates of varying thicknesses suspended by thin, flexible polyimide arms has been developed. The process uses bulk micromachining techniques and consists of four steps: a diaphragm etch from the back of the wafer; a trench etch from the front side (to define the plates); deposition and patterning of the plate support beams; and a self-aligned backside plasma etch to release the plates. The authors have used this process to fabricate square silicon plates two millimeters on a side and 7-10- mu m-thick suspended by polyimide beams 500- mu m long, 4- mu m thick, and 100-200- mu m wide. By evaporating aluminum on the topside of the plates, it was possible to deflect them electrostatically approximately 60 mu m at 40 V applied voltage. These structures were designed for application as micromachined mirrors, although their sensitivity to motion and electrical and thermal isolation suggest other potential applications such as gas sensors, flow sensors, and accelerometers.< >

关键词： Fabrication Silicon Etching Polyimides Gas detectors Arm Micromachining Particle beams Plasma applications Aluminum

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An In/sub 0.52/Al/sub 0.48/As/n/sup +/-In/sub 0.53/Ga/sub 0.47/As MISFET with a modulation-doped channel

IEEE Electron Device Letters

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IEEE Electron Device Letters 1989年第8期10卷 394-396页

作者： J.A. del Alamo T. Mizutani NTT LSI Laboratories Atsugi Japan Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology Cambridge MA USA

A heterostructure metal-insulator-semiconductor field-effect transistor (MISFET) with a modulation-doped channel is proposed. In this device, a very thin undoped subchannel is located between the undoped wide-bandgap insulator and a thin heavily doped channel. In the depletion mode of operation, electron transport takes place along the heavily doped channel. When the device enters the accumulation mode of operation, electrons pile up against the heterointerface in the high-mobility undoped subchannel. This results in markedly improved transport characteristics at the onset of accumulation. The concept is demonstrated in the In/sub 0.52/Al/sub 0.48/As/In/sub 0.53/Ga/sub 0.47/As system on InP. A 1.5- mu m-gate-length MISFET shows a unity current-gain cutoff frequency of 37 GHz.< >

关键词： MISFETs Epitaxial layers HEMTs MODFETs Insulation Substrates Electrons Indium phosphide FETs Metal-insulator structures

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Boolean minimization and algebraic factorization procedures for fully testable sequential machines

Boolean minimization and algebraic factorization procedures ...

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IEEE International Conference on computer-Aided Design

作者： S. Devadas K. Keutzer Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology Cambridge USA AT and T Bell Laboratories Murray Hill NJ USA

The authors present a novel Boolean minimization procedure of prime-implicant generation and constrained covering based on the Quine-McCluskey algorithm. On completion, it guarantees a prime and irredundant, fully testable Moore or Mealy finite state machine. Given a two-level circuit with these properties, constrained algebraic factorization techniques are used that retain the invariant that no single fault can both produce an invalid state and corrupt the distinguishing sequence by which that invalid state is detected. Besides offering a more detailed understanding of the sources of untestability in sequential circuits than previous approaches, this approach offers significant practical advantages as well. It is applicable to a wider range of circuits than optimal synthesis procedures whose utility is often limited by prohibitively high CPU requirements, and its less restrictive synthesis constraints result in lower area overhead than other constrained synthesis approaches. These observations are supported by experimental results.< >

关键词： Minimization Sequential analysis Circuit testing Logic testing Circuit faults Logic circuits Paper technology Rails Feedback Radio access networks

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Drastically improved performance in poly-Si TFTs with channel dimensions comparable to grain size

Drastically improved performance in poly-Si TFTs with channe...

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International Electron Devices Meeting (IEDM)

作者： N. Yamauchi J.-J. Hajjar R. Reif NTT Applied Electronics Laboratories Tokyo Japan Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology Cambridge MA USA

Poly-Si thin-film transistors (TFTs) with channel dimensions (width, W, and length, L) comparable to the grain size of the film were fabricated and characterized. The grain size of the film was enhanced by Si ion implantation followed by a low-temperature anneal. A remarkable improvement was observed in the device performance as the channel dimensions decreased to W=L=2 mu m. The TFTs with submicron channel dimensions were characterized by an extremely abrupt switching in their transfer characteristic. The improvement was attributed to the floating-body effect as well as the minimization of the grain boundary effect. It is believed that the results obtained will have impact in the development of large-area devices such as active-matrix liquid-crystal displays and image sensors with on-glass circuits.< >

关键词： Thin film transistors Grain size Semiconductor films Ion implantation Annealing Minimization Grain boundaries Active matrix liquid crystal displays Image sensors Circuits

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A DIGITAL READOUT TECHNIQUE FOR CAPACITIVE SENSOR APPLICATIONS

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IEEE JOURNAL OF SOLID-STATE CIRCUITS 1988年第4期23卷 972-977页

作者： KUNG, JT LEE, HS HOWE, RT IEEE Microsystems Technology Laboratories Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology

The difference between two capacitors is measured digitally using a charge redistribution technique incorporating a comparator, MOS switches, a successive approximation register, and a digital-to-analog converter. The technique is insensitive to comparator offset and parasitic capacitance, and the effect of MOS switch charge injection is measured and canceled. Extensive measurements have been made from test chips fabricated in 3- mu m CMOS technology. Detection of percent differences of >0.5% on 20-100-fF capacitors has been successfully demonstrated.

关键词： mos Oncogenes Parasitic capacitance Capacitors Percent digital to analog converters COMPARATORS test chip METAL OXIDE SEMICONDUCTORS successive approximation register digitally Switches charge injection

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Surface-micromachining processes for electrostatic microactuator fabrication

Surface-micromachining processes for electrostatic microactu...

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IEEE Workshop on Solid-State Sensor and Actuator

作者： T.A. Lober R.T. Howe Department of Electrical Engineering and Computer Science Microsystems Technology Laboratories Massachusetts Institute of Technology Cambridge MA USA Berkeley Sensor & Actuator Center Department of Electrical Engineering and Computer Sciences University of California Berkeley CA USA

Etch characteristics are discussed of three forms of hydrofluoric acid, used as the micromachining etchant for fabricating a rotary variable-capacitance micromotor structure from polycrystalline silicon (poly-Si) thin films. Low-pressure chemically vapor deposited SiO/sub 2/ (LPCVD LTO) is used to form the sacrificial layers and LPCVD Si/sub 3/N/sub 4/ is used as an electrical isolation layer for the micromachined structure. 7:1, NH/sub 4/F:HF buffered HF (BHF), 48 wt.% concentrated hydrofluoric acid (LHF), and HF vapor in air (VHF) are evaluated at 20 degrees C for etch rate and selectivity, and attack of four types of LPCVD poly-Si films; POCl/sub 3/-doped or undoped, with or without 1150 degrees C annealing. Both BHF and VHF are found to damage POCl/sub 3/-doped poly-Si films, possibly by attack of grain boundaries. VHF is found to be effective for micromachining suspended structures since it avoids deformation of microstructures due to surface tension effects during drying after wet etching with LHF or BHF.< >

关键词： Electrostatics Microactuators Etching Micromachining Hafnium Micromotors Silicon Semiconductor thin films Chemicals Semiconductor films

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A thermally isolated microstructure suitable for gas sensing applications

A thermally isolated microstructure suitable for gas sensing...

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IEEE Workshop on Solid-State Sensor and Actuator

作者： M.A. Huff S.D. Senturia R.T. Howe Microsystems Technology Laboratory Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology Cambridge MA USA Berkeley Sensors and Actuator Center Department of Electrical Engineering and Computer Sciences University of California Berkeley CA USA

A thermally isolated microstructure for use in metal-oxide gas sensing applications was fabricated and tested. Using the techniques of bulk micromachining, a thin silicon membrane 5 mu m thick was fabricated and then used as a structural support during subsequent device processing. The mechanical stability of the thin silicon membrane was found to be dependent on the compressive surface-oxide thickness which induced membrane buckling. A study of the buckling criteria was examined in detail by performing etch-back experiments on a series of sequentially sized membranes and observing the transition for buckling. A linear relationship between oxide thickness and membrane edge length squared was found. The device is fabricated over the membrane on the wafer surface and consists of a sandwich of LPCVD Si/sub 3/N/sub 4/, LPCVD poly-Si and LPCVD Si/sub 3/N/sub 4/. After device fabrication, the support membranes is etched away leaving the device completely isolated from the substrate. The measured values of power consumption and thermal time constant are compared with a simple model.< >

关键词： Microstructure Biomembranes Silicon Etching Testing Micromachining Stability Fabrication Power measurement Time measurement

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High speed interconnection using the clos network 1st

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1st International Conference on Supercomputing, 1987

作者： Payne, William A. Makedon, Fillia Daasch, W. Robert AT&T Bell Laboratories NapervilleIL60566 United States Illinois Institute of Technology ChicagoIL60616 United States Department of Computer Science University of Texas-Dallas RichardsonTX75083-0688 United States Depamnent of Electrical Engineering Portland State University PortlandOR97207 United States

ISBN: (纸本)9783540189916

This paper discussed two aspects of the use of the Clos networks for high capacity statistical switching. A self routing algorithm was described for the general s staged Clos network, as well as for a special case of the Clos network for which the routing is simpler. The topological VLSI area complexity of the Clos network was also studied and was found to be comparable in many instances to that of the crossbar network. This is true even though the number of crosspoints in the Clos network is usually less than that of the crossbar. © 1988, Springer-Verlag.

关键词： Interconnection networks (circuit switching)

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What is the path to fast fault simulation?

What is the path to fast fault simulation?

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IEEE International Test Conference

作者： M. Abramovici B. Krishnamurthy R. Mathews B. Rogers M. Schulz S. Seth J. Waicukauski AT and T Information Systems Inc. Naperville IL USA Tektronix Laboratories Beaverton OR USA Zycad Limited Menlo Park CA USA Department of Electrical & Computer Engineering University of Technology Austin TX USA Institute of CAD Department of Electrical Engineering Technical University Munich Munich Germany Department of Computer Science University of Nebraska Lincolnshire NE USA IBM Corporation Hopewell Junction NY USA

Motivated by the advances in fast fault-simulation techniques for large combinational circuits, a panel discussion was organized for the 1988 International Test Conference. A collective account of the position statements is offered by the panelists. The panelists present discussions on the following topics: introduction to fault simulation; parallel pattern fault simulation; intelligent heuristics; graph-theoretic approaches; approximate solutions; hierarchical fault simulation; and hardware solutions.< >

关键词： Circuit faults Circuit testing Circuit simulation Computational modeling Combinational circuits electrical fault detection Sequential circuits Fault detection Logic testing laboratories

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NOVEL MICROSTRUCTURES FOR THE INSITU MEASUREMENT OF MECHANICAL-PROPERTIES OF THIN-FILMS

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JOURNAL OF APPLIED PHYSICS 1987年第9期62卷 3579-3584页

作者： MEHREGANY, M HOWE, RT SENTURIA, SD Microsystems Technology Laboratories Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology Cambridge Massachusetts 02139

This paper discusses microfabricated structures designed for the i n s i t u measurement of the mechanical properties of thin films under residual tensile stress. The film is deposited and patterned on a (100) silicon substrate in which 5‐μm‐thick diaphragms have been fabricated. When the silicon diaphragm is etched from the backside in an SF₆ plasma, the microstructures are released and deform under the residual tension. Measurement of this deformation in conjunction with appropriate mechanical models determines the mechanical properties of interest. We have used these structures to study benzophenonetetracarboxylicdianhidride‐oxydianiline/metaphenylene‐diamine polyimide films. Typical value for the residual stress to modulus ratio in this case was determined to be 0.011±0.001 while the ultimate strain at break was found to be 4.5% for 5.5‐μm‐thick films. For thicker films (8.5 μm), the film did not fail until 8% strain was reached.

关键词： Thin film structure Mechanical properties Silicon Thin film deposition Microstructural properties

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