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检索条件"机构=Mixed Signal Circuit Design"

共 199 条记录，以下是1-10 订阅

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An 11-Bit 12 GS/s Beam-Forming Receiver ADC for a 2x2 Antenna Array utilizing True Time-Delay with 68 dBc SFDR and 55 dB SNDR

An 11-Bit 12 GS/s Beam-Forming Receiver ADC for a 2x2 Antenn...

引用

IEEE International Symposium on circuits and Systems (ISCAS)

作者： Wittenhagen, Enne Wilding, Dominik Kurth, Patrick Linnhoff, Sebastian Buballa, Frowin Hecht, Urs Artz, Patrick Gerfers, Friedel Tech Univ Berlin Mixed Signal Circuit Design Berlin Germany

ISBN: (纸本)9798350330991;9798350331004

This paper presents an 11-bit 12 GS/s 4x timeinterleaved beam-forming ADC for a 2x2 antenna array in a 22nm FDSOI CMOS process. The RF-input is buffered with a push-pull source-follower providing both high linearity and high-bandwidth. The receiver utilizes sample-based beam-forming with a true time-delay generated from a clock delay network with uniform 11.9 ps time-steps. Thus, all inputs are sampled phase-aligned without any phase-shifter in the RF-path. A chargebased summation enables a low-power beam-forming functionality without any wave-length dependencies. The summed output is buffered by a push-pull back-end buffer with cascodes providing a high-linearity. In total, 24x 11-bit 500 MS/s SAR subADCs digitize the summed output of the beam-former. Time-interleave sample-phase mismatch can be calibrated with a 30 fs step-size. The ADC achieves a voltage gain of 8.55 dB in steering direction. An overall SFDR and SNDR above 68 dBc and 55 dB respectively is achieved. Only a total of 99.5mW per antenna is drawn.

关键词： beam-forming analog-beam-forming ADC 2x2 receiver track-and-hold time-interleaved

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A Wide Band High Linearity CT-ΣΔ Converter for Receivers Reaching 1.75 Gb/s Using 16384 QAM 15

A Wide Band High Linearity CT-ΣΔ Converter for Receivers R...

引用

15th German Microwave Conference (GeMiC)

作者： Edler, Julius Artz, Patrick James Wittenhagen, Enne Gerfers, Friedel Tech Univ Berlin Chair Mixed Signal Circuit Design Berlin Germany

ISBN: (纸本)9783982039732

Higher order quadrature amplitude modulation (QAM) schemes enable increased data rates as well as improved spectral efficiency and thereby empower the evolution of future mobile communication standards. A key component in the receive chain is the analog-to-digital converter (ADC). Performance metrics are usually extracted using narrow-band signals such as high-purity single or two-tone sine waves. As an alternative, this paper describes gigabit rate receiver characterizations using complex wide-band signals with modulation depths up to 16384-QAM. This is possible by the use of a wide-band Sigma-Delta ADC with > 60 dB dynamic range with a bandwidth of 250 MHz. The complete digital signal processing chain is described, which features a linear equalizer and a low-pass decimation filter to recover the transmitted symbols. The influence of various transceiver design choices, such as the pulse shaping filter are measured. For the mitigation of interference from of out-of-band signals, high linearity is essential. This is shown by a sine-wave interference test showing RMS error-vector-magnitudes (EVM) under different linearity conditions. Here, EVMs of less than 0.2% are presented with 1.75 Gb/s transmission speed enabling future mobile communications.

关键词： ADC wide band Sigma delta 16384 QAM modulation pulse shaping linear equalizer error vector magnitude linearization mobile communication data converter

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A 16 GS/s Voltage-to-Time Conversion Sampler with 35.9 dB SNDR in 22 nm CMOS FDSOI

A 16 GS/s Voltage-to-Time Conversion Sampler with 35.9 dB SN...

引用

IEEE International Symposium on circuits and Systems (ISCAS)

作者： Misselwitz, Kai Gerfers, Friedel Tech Univ Berlin Chair Mixed Signal Circuit Design Berlin Germany

ISBN: (纸本)9798350330991;9798350331004

This work presents a 16 GS/s voltage-to-time conversion sampler architecture reaching an SNDR of 35.9 dB with a bandwidth of 17 GHz. Operating from a single 0.7V supply consuming 6mW of power. The sampler inherently performs a voltage-to-time conversion, enabling the use of power-efficient time-to-digital converters for further processing. The design is based on a CMOS inverter delay which is modulated by the input signal. In addition to the low power usage, it features a high input impedance compared to a conventional sampler where the input capacitance is determined by the noise target. In this paper a nonlinearity model for this circuit is derived and a prototype is implemented in a 22nm CMOS FDSOI. The entire design is evaluated through SPICE simulations of the extracted layout.

关键词： Capacitance

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Energy-efficient D-Band Power Amplifier Linearization Adopting Back-Gate Feedforward Technique in 22nm FD-SOI

Energy-efficient D-Band Power Amplifier Linearization Adopti...

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IEEE Topical Conference on RF/Microwave Power Amplifiers for Radio and Wireless Applications (PAWR)

作者： Ordouei, Helia Gerfers, Friedel Tech Univ Berlin Chair Mixed Signal Circuit Design Berlin Germany

ISBN: (纸本)9798350314649

This work presents a highly energy-efficient linearization technique for D-band power amplifiers (PA) in 22nm fully-depleted silicon-on-insulator (FD-SOI) technology. The nonlinear effects arising from the NMOS transistor transconductance are reduced by leveraging the back-gate terminal of the output stage devices, directly controlling the biasing point based on the input RF signal. A 2-stage PA has been designed to demonstrate the effectiveness and robustness of the proposed technique. The prototype 22nm FD-SOI CMOS PA delivers 10.2dB peak power gain, >11dBm saturated power (Psat) and a power-addedefficiency (PAE) of 6% at the 1dB output compression point (OP1dB) with an 0.8V supply centered at a carrier frequency of 150GHz. The adaptive back-gate feedforward loop improves the overall input 1dB compression point by 2.5dB while at the same time decreasing the third- and 5th-order intermodulation distortions across the entire bandwidth by 6dB and 10dB, respectively. Furthermore, the EVM is improved by 5.5 and 6.1 percentage points for a 10-MHz 5G NR 16-QAM and a 64-QAM signal, respectively.

关键词： D-band Back-Gate (BG) FD-SOI technology power amplifier linearization 6G mobile communication

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A 12 GS/s RF-Sampler Employing Inductive Peaking in 22 nm FD-SOI CMOS 18

A 12 GS/s RF-Sampler Employing Inductive Peaking in 22 nm FD...

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18th European Microwave Integrated circuits Conference (EuMIC)

作者： Wittenhagen, Enne Kurth, Patrick Lotfi, Nima Hecht, Urs Edler, Julius Scholz, Philipp Gerfers, Friedel Tech Univ Berlin Mixed Signal Circuit Design Berlin Germany

ISBN: (纸本)9782874870736

This paper presents a 12 GS/s RF-sampler in 22nm FD-SOI CMOS. An RF-impedance matched FE-buffer drives the proposed track-and-hold circuit. For the first time, inductive peaking is utilized inside a track-and-hold to increase the bandwidth over 23% from initially 12.9 GHz to 15.9 GHz compared to an un-peaked sampler without consuming additional power. No time-interleaving is utilized, eliminating the need for calibration of gain/offset/sample-phase mismatches. The RF-sampler maintains a SFDR and SNR above 53 dB and 49.8 dB, respectively, across the entire Nyquist band. A high frequency SNR improvement of 1.5 dB is simulated. The proposed RF-sampler is insensitive to input common-mode as well as supply voltage variations. The simulated clock jitter is only 22 fs, which does not degrade the high-frequency SNR. A total power consumption of only 58mW is required from a 1.2V and 0.9V supply.

关键词： track-and-hold FD-SOI inductive peaking RF sampling

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A mmw Low-Noise Sub-Sampling Phase-Locked Loop with a Non-Pulsed Charge Pump, Frequency Calibration and a Compact Ultra-High-Q Resonator

A mmw Low-Noise Sub-Sampling Phase-Locked Loop with a Non-Pu...

引用

IEEE International Symposium on circuits and Systems (ISCAS)

作者： Kurth, Patrick Scholz, Philipp Nickel, Philip Hecht, Urs Wittenhagen, Enne Misselwitz, Kai Gerfers, Friedel Tech Univ Berlin Mixed Signal Circuit Design Einsteinufer 17 D-10587 Berlin Germany

ISBN: (纸本)9798350330991;9798350331004

This paper presents the architecture and implementation of a low-noise sub-sampling phase-locked loop (SSPLL) for mm-wave frequencies. It leverages an LC oscillator with a novel resonator, a digital lock assist and frequency calibration system as well as a novel charge pump implementation. The charge pump eliminates the pulser and runs continuously, which significantly reduces its power consumption while maintaining equal noise performance. The calibration system solves the lock problem of the SSPLL by implementing a lock/frequency search to prevent non- and false-lock. The LC oscillator employs an optimized resonator which combines both the inductor and the capacitor on the same metal, resulting in a very high quality factor by eliminating the interconnect resistance within the resonator. The SSPLL was implemented and simulated in a 22-nm-FDSOI technology, alongside with measurement results of the LC oscillator, which was fabricated in the same technology.

关键词： Sub-Sampling Phase-Locked Loop Millimeter-Wave (mm-Wave) Frequency Calibration Lock Assist High-Q Resonator

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A Digital Pre-Distortion Technique Canceling Code-and Voltage-Dependent Output Impedance Errors in Current-Steering DACs 56

A Digital Pre-Distortion Technique Canceling Code-and Voltag...

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56th IEEE International Symposium on circuits and Systems (ISCAS)

作者： Ordouei, Helia Alija, Clirim Kurth, Patrick Gerfers, Friedel Tech Univ Berlin Chair Mixed Signal Circuit Design Berlin Germany

ISBN: (纸本)9781665451093

This paper presents a 12-bit segmented digital-toanalog converter (DAC) with small size high linearity noncascoded current cells. A pre-distortion calibration technique, using a low-complexity lookup table, is proposed to cancel the third order code-dependent nonlinearity induced by low output impedance of unary current cells. Based on a detailed mathematical analysis, the coefficients of the digital pre-filter are deducted. In addition, the body biasing technique in 22FDX technology is employed to adaptively tune the back-gate voltage of each current source via an auxiliary DAC to reduce mismatch errors. The current-steering (CS) DAC achieves >74dBc spuriousfree dynamic range (SFDR) and >11 effective number of bits (ENOB) over the entire Nyquist bandwidth at 1GS/s and across process and temperature corners. The implementation enables a small area and compact layout of the unary cells, low-power consumption from a dual 0.8/1.2V power supply and a 1-Vppd output signal swing without the use of cascode structures.

关键词： Current-steering digital-to-analog converter (DAC) Linearization output impedance body-biasing 22FDX

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A 4 GBaud 5 Vpp Class-B Pre-Driver design for GaN-Based Switching Power Amplifier in 22 nm SOI-CMOS Utilizing LDMOS 21

A 4 GBaud 5 Vpp Class-B Pre-Driver Design for GaN-Based Swit...

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21st IEEE Interregional NEWCAS Conference (NEWCAS)

作者： Buballa, Frowin Linnhoff, Sebastian Wittenhagen, Enne Hecht, Urs Gerfers, Friedel Tech Univ Berlin Chair Mixed Signal Circuit Design Berlin Germany

ISBN: (纸本)9798350300246

The paper presents a highly power efficient class-B LDMOS-based pre-driver, implemented in a 22nm FDSOI CMOS process. The driver generates an output voltage swing of 5.5V at a data-rate of 4 GBaud for GaN-based switching power amplifier with an estimated capacitive load impedance of 0.35 pF. This is achieved by utilizing monolithical integrated LDMOS devices with a breakdown voltage of 6.5V, available in the deep submicron state-of-the-art CMOS process, which are driven by an inverter-chain consisting of 2V thick-oxide devices with an active back-gate control to implement a duty-cycle calibration. The proposed design achieves rise- and fall-times of 70 ps and 40 ps, respectively. The total power consumption is below 140mW from a triple 5.5V, 3.5V and 2V power supply for a 4 GBaud NRZ PRBS input. This greatly improves the state-of-the-art power efficiency for CMOS-based GaN power amplifier pre-driver.

关键词： CMOS 22nm FDSOI LDMOS back-gate control GaN gate driver digital power amplifier

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A 10 Bit 6 GS/s Time-Interleaved SAR ADC with a Single Full-Rate Front-End Track-and-Hold 21

A 10 Bit 6 GS/s Time-Interleaved SAR ADC with a Single Full-...

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21st IEEE Interregional NEWCAS Conference (NEWCAS)

作者： Linnhoff, Sebastian Buballa, Frowin Edler, Julius Wittenhagen, Enne Hecht, Urs Gerfers, Friedel Tech Univ Berlin Chair Mixed Signal Circuit Design Berlin Germany

ISBN: (纸本)9798350300246

This paper presents an ultra-wideband 10 bit 6 GS/s time-interleaved successive approximation register (SAR) analog-to-digital converter (ADC) implemented in a standard 28nm CMOS technology. The single front-end top-plate track-and-hold circuit (T/H) provides 17.4 GHz sampling bandwidth, > 70 dB linearity in spite of the 75 ps tracking duration and adequate kickback isolation while driving twelve 500 MS/s SAR-ADC lanes. Utilizing a full-rate front-end sampler at 6 GS/s simplifies the overall ADC calibration scheme as both, timing- and bandwidth mismatch are eliminated. Each SAR-ADC lane takes advantage of a capacitive sub-2 radix digital-to-analog converter (C-DAC) topology with 6.5% overrange to handle C-DAC mismatch effects as well as finite settling while a fully loop-unrolled comparator architecture with multiple latches maximizes the sampling rate and linearity. The SAR-ADC system operates from a 2.5V/ 1.8V/ 1V/ -1.3V power supply consuming in total 1.2W. The ADC achieves an excellent spectral performance with a SNDR and SFDR of 54.8 dB and 69.5 dBc respectively, using a single full scale 1Vppd sine wave tone close to Nyquist frequency after C-DAC mismatch, time-interleaved gain and offset mismatch calibration.

关键词： Nyquist-ADC Time-interleaving timing-mismatch high-speed ADC

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A 2.41-μW/MHz, 437-PE/mm² CGRA in 22 nm FD-SOI With RISC-Like Code Generation 26

A 2.41-μW/MHz, 437-PE/mm<SUP>2</SUP> CGRA in 22 nm FD-SOI W...

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26th IEEE International Symposium on Low-Power and High-Speed Chips (COOL CHIPS)

作者： Kaiser, Tobias Gerfers, Friedel Tech Univ Berlin Chair Mixed Signal Circuit Design Berlin Germany

ISBN: (纸本)9798350332018

While coarse-grained reconfigurable arrays (CGRAs) have the potential to improve energy efficiency in general-purpose computing beyond the limitations of von Neumann architectures, they suffer from challenges in code generation. Pasithea-1 is a CGRA architecture that aims to combine high energy efficiency with RISC-like programmability. This paper presents its first silicon prototype and a C compiler that uses conventional CPU compiler techniques. Compared to code generation for traditional CGRAs, which require expensive place and route steps, this method of code generation reduces compile times and compiler complexity significantly. Performance and power were measured for a set of benchmark programs written in C. On average, energy efficiency of 195.1 int32 MIPS/mW and active power of 2.41 mu W/MHz were achieved. Peak energy efficiency of 558.2 MIPS/mW and peak performance of 97.5 MIPS were measured. Load/store instructions and instruction transfers are identified as critical factors for energy efficiency in Pasithea. In comparison to an MCU with state-of-the-art energy efficiency, Pasithea achieves higher energy efficiency in four of the benchmarked programs. Switched capacitance per benchmark run was reduced by a factor of approximately 1.4, on average. Its 0.75 mm(2) core area and fabric density of 437 PEs/mm(2) enable use in cost-sensitive applications and permit further upscaling.

关键词： Energy efficiency

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