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检索条件"机构=Mobile Computing and Compilers"

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Mis-speculation-driven compiler framework for aggressive loop automatic parallelization

Mis-speculation-driven compiler framework for aggressive loo...

引用

2013 IEEE 37th Annual Computer Software and Applications Conference, COMPSAC 2013

作者： Lin, Jin Tian, Xinmin Ng, John Mobile Computing and Compilers Intel Corporation Santa CA 95052 United States

ISBN: (纸本)9780769549798

Large real world applications with irregular control-flow and/or data-flow pose challenges on the progressive improvement of state-of-The-Art optimizing compilers. These irregular control-flow and data-flow are often not compile-time analyzable, and had inhibited important loop optimizations such as parallelization and vectorization. Conventional compiler techniques on parallelizing loops with such irregular control-flow and/or data-flow have mainly focused on eliminating the loop carried control-flow or data-flow dependencies. The issue to effectively enable both control and data speculation for different loop optimizations remains open. This paper proposes a new unified compiler framework which takes both control and data speculation into account to enable more aggressive loop optimizations including loop parallelization, loop vectorization, loop fusion and loop distribution through mis-speculation-driven loop splitting. Our main ideas are: i) unifying control and data speculation in the compiler framework to enable more loop optimizations;ii) performing lazy inspection code generation based on speculation guards to enable later compiler analyses and optimizations without requiring any change to accommodate the speculative information;iii) driving loop splitting using the unified mis-speculation information generated by the inspection code to enable more loops being parallelized. The proposed techniques and framework have been implemented in Intel's product compiler. Our experimental results show that the new techniques yield significant performance gains from 35% to 62% on some SPEC CPU2006 benchmarks. © 2013 IEEE.

关键词： Inspection

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Compiling C/C++ SIMD extensions for function and loop vectorizaion on multicore-SIMD processors

Compiling C/C++ SIMD extensions for function and loop vector...

引用

2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2012

作者： Tian, Xinmin Saito, Hideki Girkar, Milind Preis, Serguei V. Kozhukhov, Sergey S. Cherkasov, Aleksei G. Nelson, Clark Panchenko, Nikolay Geva, Robert Mobile Computing and Compilers Software and Service Group Intel Corporation Santa Clara CA United States

ISBN: (纸本)9780769546766

SIMD vectorization has received significant attention in the past decade as an important method to accelerate scientific applications, media and embedded applications on SIMD architectures such as Intel® SSE, AVX, and IBM* AltiVec. However, most of the focus has been directed at loops, effectively executing their iterations on multiple SIMD lanes concurrently relying upon program hints and compiler analysis. This paper presents a set of new C/C++ high-level vector extensions for SIMD programming, and the Intel® C++ product compiler that is extended to translate these vector extensions and produce optimized SIMD instruction sequences of vectorized functions and loops. For a function, our main idea is to vectorize the entire function for callers instead of just vectorizing loops (if any) inside the function. It poses the challenge of dealing with complicated control-flow in the function body, and matching caller and callee for SIMD vector calls while vectorizing caller functions (or loops) and callee functions. Our compilation methods for automatically compiling vector extensions are described. We present performance results of several non-trivial visual computing, computational, and simulation workloads, utilizing SIMD units through the vector extensions on Intel® Multicore 128-bit SIMD processors, and we show that significant SIMD speedups (3.07x to 4.69x) are achieved over the serial execution. © 2012 IEEE.

关键词： Vectors

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Practical SIMD vectorization techniques for Intel® Xeon Phi coprocessors

Practical SIMD vectorization techniques for Intel® Xeon Phi...

引用

2013 IEEE 37th Annual Computer Software and Applications Conference, COMPSAC 2013

作者： Tian, Xinmin Saito, Hideki Preis, Serguei V. Garcia, Eric N. Kozhukhov, Sergey S. Masten, Matt Cherkasov, Aleksei G. Panchenko, Nikolay Mobile Computing and Compilers Software and Service Group Intel Corporation Santa Clara CA United States Novosibirsk Russia

ISBN: (纸本)9780769549798

Intel® Xeon Phi coprocessor is based on the Intel® Many Integrated Core (Intel® MIC) architecture, which is an innovative new processor architecture that combines abundant thread parallelism with long SIMD vector units. Efficiently exploiting SIMD vector units is one of the most important aspects in achieving high performance of the application code running on Intel® Xeon Phi coprocessors. In this paper, we present several practical SIMD vectorization techniques such as less-than-full-vector loop vectorization, Intel® MIC specific alignment optimization, and small matrix transpose/multiplication 2-D vectorization implemented in the Intel® C/C++ and Fortran production compilers for Intel® Xeon Phi coprocessors. A set of workloads from several application domains is employed to conduct the performance study of our SIMD vectorization techniques. The performance results show that we achieved up to 12.5x performance gain on the Intel® Xeon Phi coprocessor. © 2013 IEEE.

关键词： Coprocessor

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Compiling C/C++ SIMD Extensions for Function and Loop Vectorizaion on Multicore-SIMD Processors

Compiling C/C++ SIMD Extensions for Function and Loop Vector...

引用

IEEE International Symposium on Parallel and Distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Xinmin Tian Hideki Saito Milind Girkar Serguei V. Preis Sergey S. Kozhukhov Aleksei G. Cherkasov Clark Nelson Nikolay Panchenko Robert Geva Mobile Computing and Compilers Software and Service Group Intel Corporation Santa Clara CA USA Software and Service Group Mobile Computing and Compilers Intel Corporation Novosibirsk Russia

ISBN: (纸本)9781467309745

SIMD vectorization has received significant attention in the past decade as an important method to accelerate scientific applications, media and embedded applications on SIMD architectures such as Intel ® SSE, AVX, and IBM* AltiVec. However, most of the focus has been directed at loops, effectively executing their iterations on multiple SIMD lanes concurrently relying upon program hints and compiler analysis. This paper presents a set of new C/C++ high-level vector extensions for SIMD programming, and the Intel ® C++ product compiler that is extended to translate these vector extensions and produce optimized SIMD instruction sequences of vectorized functions and loops. For a function, our main idea is to vectorize the entire function for callers instead of just vectorizing loops (if any) inside the function. It poses the challenge of dealing with complicated control-flow in the function body, and matching caller and callee for SIMD vector calls while vectorizing caller functions (or loops) and callee functions. Our compilation methods for automatically compiling vector extensions are described. We present performance results of several non-trivial visual computing, computational, and simulation workloads, utilizing SIMD units through the vector extensions on Intel ® Multicore 128-bit SIMD processors, and we show that significant SIMD speedups (3.07x to 4.69x) are achieved over the serial execution.

关键词： Vectors Graphics processing unit Hardware Programming Parallel processing Cloning

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Practical SIMD Vectorization Techniques for Intel® Xeon Phi Coprocessors

Practical SIMD Vectorization Techniques for Intel® Xeon Phi...

引用

IEEE International Symposium on Parallel and Distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Xinmin Tian Hideki Saito Serguei V. Preis Eric N. Garcia Sergey S. Kozhukhov Matt Masten Aleksei G. Cherkasov Nikolay Panchenko Mobile Computing and Compilers Software and Service Group Intel Corporation Santa Clara California USA Mobile Computing and Compilers Software and Service Group Intel Corporation Novosibirsk Russia

关键词： Vectors Coprocessors Microwave integrated circuits Optimization Registers Computer architecture Parallel processing

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Mis-speculation-Driven Compiler Framework for Aggressive Loop Automatic Parallelization

Mis-speculation-Driven Compiler Framework for Aggressive Loo...

引用

IEEE International Symposium on Parallel and Distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Jin Lin Xinmin Tian John Ng Mobile Computing and Compilers Intel Corporation Santa CA U.S.A

ISBN: (纸本)9781479913725

Large real world applications with irregular control-flow and/or data-flow pose challenges on the progressive improvement of state-of-the-art optimizing compilers. These irregular control-flow and data-flow are often not compile-time analyzable, and had inhibited important loop optimizations such as parallelization and vectorization. Conventional compiler techniques on parallelizing loops with such irregular control-flow and/or data-flow have mainly focused on eliminating the loop carried control-flow or data-flow dependencies. The issue to effectively enable both control and data speculation for different loop optimizations remains open. This paper proposes a new unified compiler framework which takes both control and data speculation into account to enable more aggressive loop optimizations including loop parallelization, loop vectorization, loop fusion and loop distribution through mis-speculation-driven loop splitting. Our main ideas are: i) unifying control and data speculation in the compiler framework to enable more loop optimizations; ii) performing lazy inspection code generation based on speculation guards to enable later compiler analyses and optimizations without requiring any change to accommodate the speculative information; iii) driving loop splitting using the unified mis-speculation information generated by the inspection code to enable more loops being parallelized. The proposed techniques and framework have been implemented in Intel's product compiler. Our experimental results show that the new techniques yield significant performance gains from 35% to 62% on some SPEC CPU2006 benchmarks.

关键词： Optimization Inspection Arrays Indexes Program processors mobile computing Parallel processing

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Performance Study of SIMD Programming Models on Intel Multicore Processors

Performance Study of SIMD Programming Models on Intel Multic...

引用

IEEE International Symposium on Parallel and Distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Peter Kristof Hongtao Yu Zhiyuan Li Xinmin Tian Department of Computer Science Purdue University West Lafayette IN USA Mobile Computing and Compilers SSG Intel Corporation Santa Clara CA USA

ISBN: (纸本)9781467309745

Modern multicore hardware employs a variety of parallel execution units, including multiple CPU cores for executing multiple threads simultaneously, vector units such as the Intel SIMD on the CPU cores, as well as GPU-like processing arrays. Availability of such unprecedented level of parallelism on main-stream computers offers an enormous potential to enable a new generation of computation-intensive nontraditional applications. On the other hand, how to best harness the hardware parallelism presents a new challenge to application programmers, language designers and compiler developers. In this paper, we evaluate the impact of several different parallel execution models, especially the new SIMD vectorization methods, supported by the latest Intel ICC compiler (version 12.1), using three computation-intensive nontraditional parallel applications as the test workload. Unlike traditional numerical programs, these applications use highly irregular data structures and therefore present nontrivial challenges to effective use of SIMD vector units. The first application is a game engine architecture requiring real-time performance. The second application involves a kd-tree traversal, which is typical to the state-of-the-art 3D ray-tracing applications. The last application processes data for large-scale weather visualization system in the order of tens of minutes. We compare the execution time of these codes using different SIMD models supported by ICC in conjunction with parallel threading under TBB and OpenMP.

关键词： Vectors Games Program processors Parallel processing Engines Benchmark testing Computational modeling

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