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IEEE Conference on Wireless Communications and Networking

作者： Sangkil Jung Sangjin Hong Mobile Systems Design Laboratory Department of Electrical and Computer Engineering Stony Brook University-SUNY Stony Brook NY USA

Assured forwarding per-hop behavior (AF PHB) is a forwarding scheme for providing QoS in DiffServ networks. It defines four classes and three drop precedence, where buffer space and bandwidth are defined as forwarding resources for each AF class (J. Heinanen et al., 1999). RIO (D.D. Clark and W. Fang, 1998) could be used as drop policy in a DiffServ router. AF PHB could be implemented by WRR, WFQ, CBQ, etc. When network managers provide AF PHB using the scheduling mechanisms, they want to guarantee accurate achievement of service expectation level, which results from precise queue weight allocation to each AF class with respect to forwarding resources, i.e., buffer space and bandwidth. In order to provide a guideline for the precise queue weight allocation, this paper proposes a simple analytical model for AF PHB designed on RIO and M/M/1 queue, and uses this model to obtain queue weight equation (QWE), which performs fine calculation of queue weight for AF classes. Average buffer space and bandwidth allocated for each AF class are used in derivation of QWE. The model verification is performed by simulation in which we use WRR for simplicity. Simulation results show that the QWE supports an accurate allocation of the forwarding resources, and, as a result, makes four AF classes achieve fairness as well as service expectation levels

关键词： Bandwidth Queueing analysis Resource management Quality of service Diffserv networks mobile computing Laboratories Computer networks design engineering Guidelines

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VoMESH: voice over wireless MESH networks

VoMESH: voice over wireless MESH networks

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IEEE Conference on Wireless Communications and Networking

作者： Kyungtae Kim Sangjin Hong Mobile Systems Design Laboratory Department of Electrical and Computer Engineering Stony Brook University-SUNY Stony Brook NY USA

In this work, we focus on increasing network utilization to support real-time applications, especially voice over IP, in 802.11b wireless mesh network. For increasing capacity, we investigate on two directions: use of packet aggregation and utilize of header compression. Although aggregation reduces 802.11 MAC overhead, it also increases delay. We present a distributed multihop aggregation algorithm that uses the "natural" waiting time in the interface queue of packets in a loaded network. Header compression can relax the VoIP protocol overhead, but it also introduces the signaling overhead. In our work, we propose a zero-length header compression algorithm integrated with packet aggregation, which doesn't need to depend on the signaling mechanism to recover the context discrepancy between compressor and decompressor. The above performance optimization techniques are experimented in the NS2 simulator. The experimental results show an increase of 12 times for a six hop string when all optimizations are used

关键词： Wireless mesh networks Internet telephony Protocols Mesh networks Costs Delay Spread spectrum communication Telecommunication traffic Traffic control Communication system security

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Spectral Content Characterization for Efficient Image Detection Algorithm design

Spectral Content Characterization for Efficient Image Detect...

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International Conference on Computer and Information Technology (CIT)

作者： Kyoung-su Park Sangjin Hong Peom Park Mobile Systems Design Laboratory Department of Electrical and Computer Engineering Stony Brook University-SUNY Stony Brook NY USA Department of Industrial and Information Engineering Ajou University Humintec Company Limited Suwon South Korea

This paper presents spectral characterization for efficient image detection using hyperspectral processing technique. We investigate relationship between the number of bands used in the detection so that the minimum number of bands are used in the processing. This approach reduces computation and implementation complexity of the algorithms. Specifically, we considered contribution coefficient by each band and based on this coefficient, we heuristically select the bands for processing. We have shown that for effective detection, only small number of bands are needed.

关键词： Detection algorithms Algorithm design and analysis Hyperspectral imaging Hyperspectral sensors Signal processing algorithms Image edge detection Image processing Libraries Object detection mobile computing

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Tracking an Object in 3-D Space using Particle Filtering based on Sensor Array

Tracking an Object in 3-D Space using Particle Filtering bas...

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International Conference on Computer and Information Technology (CIT)

作者： Jinseok Lee Jaechan Lim Sangjin Hong Peom Park Mobile Systems Design Laboratory Department of Electrical and Computer Engineering Stony Brook University-SUNY Stony Brook NY USA Department of Industrial and Information Engineering Ajou University Humintec Company Limited Suwon South Korea

This paper presents a formulation of particle filter for tracking an object in 3-D space. The 3-D tracking algorithm is derived based on bearings only tracking algorithm that is applied in tracking of an object in 2-D space with one angle measurement. We investigate and present the fusion process of the algorithms. The performance of the proposed algorithms are evaluated in detail.

关键词： Sensor arrays Particle tracking Signal processing algorithms Particle filters Adaptive signal processing Sonar navigation Particle measurements Information filtering Information filters Gas detectors

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Effect of RObust Header Compression (ROHC) and Packet Aggregation on Multi-hop Wireless Mesh Networks

Effect of RObust Header Compression (ROHC) and Packet Aggreg...

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International Conference on Computer and Information Technology (CIT)

作者： Sangkil Jung Sangjin Hong Peom Park Mobile Systems Design Laboratory Department of Electrical and Computer Engineering Stony Brook University-SUNY Stony Brook NY USA Humintec Company Limited Suwon South Korea Department of Industrial and Information Engineering Ajou University South Korea

This paper evaluates the behavioral effect of RObust Header Compression (ROHC) and packet aggregation in multi-hop wireless mesh networks. ROHC itself shows around 20% achieved rate improvement on a line of wireless link even if as the number of mesh router increases, total achieved rate gradually decreases. Packet aggregation cooperating with ROHC provides 4 to 10 times achieved rate improvement and results in maximum 6 times reduction of end-to-end delay. Even if the ROHC and packet aggregation gives such a promising improvement, we need to identify effect of the processing time of the two schemes on overall wireless mesh network behaviors. To do this work, we measure/use ROHC processing time from Pentium 4 and RouterBOARD 230, and apply the results into NS-2 simulations. The simulation results show high performance improvement from ROHC and packet aggregation deteriorates as a general purpose processor in a mesh router takes much time to deal with the two schemes. This result motivates a hardware design be required to speed up the processing units of the two schemes. Consequently, we propose a hardware system model for ROHC and packet aggregation by using SystemC Hardware Description Language (HDL). From the SystemC results, we conclude the proposed built-in processor design for the two schemes keeps performance improvement by enhancing the low speed processing power of general purpose processors.

关键词： Robustness Spread spectrum communication Wireless mesh networks Wireless sensor networks Hardware design languages Land mobile radio cellular systems Delay IP networks Mesh networks Time measurement

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Domain specific reconfigurable processing core architecture for digital filtering applications

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Journal of VLSI Signal Processing systems for Signal, Image, and Video Technology 2005年第2期40卷 239-259页

作者： Hong, Sangjin Chin, Shu-Shin Mobile Systems Design Laboratory Dept. Elec. Comp. Eng. Stony B. Stony Brook NY 11794-2350 United States

This paper presents a reconfigurable processing core architecture targeted for digital filtering applications. The architecture can be configured to execute linear phase FIR filter, DLMS adaptive FIR filter, (I)FFT, and 2D-(I)DCT with high performance and low energy consumption by reducing heavy routing resources used extensively in other reconfigurable architectures. The pipeline depth of the multipliers in the processing core is locally controlled so that power consumption is reduced by minimizing unnecessary register switching is saved. We have shown that the proposed processing core consumes less energy and has better or comparable performance than that of the existing reconfigurable architectures proposed in academia and industry, that have been tailored for these applications. The circuit is designed in 0.35-μm CMOS processing technology with 3.3 V supply voltage. © 2005 Springer Science + Business Media, Inc.

关键词： FIR filters

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Dynamic coarse grain dataflow reconfiguration technique for real-time systems design

Dynamic coarse grain dataflow reconfiguration technique for ...

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IEEE International Symposium on Circuits and systems (ISCAS)

作者： Xiaoyao Liang A. Athalye Sangjin Hong Mobile Systems Design Laboratory Department of Electrical and Computer Engineering Stony Brook University-SUNY Stony Brook NY USA

The paper explores a reconfigurable platform design methodology for high throughput execution of data centric applications. The reconfiguration platform consists of heterogenous processing elements and buffers interacting through reconfigurable interconnects. The proposed platform is based on block level pipelining with the buffers and their respective controllers forming the pipelining elements. We discuss the dynamic and partial reconfiguration techniques of this platform. Specifically, reconfiguration overhead at runtime is illustrated.

关键词： Real time systems Switches Integrated circuit interconnections Computer architecture Pipeline processing Reconfigurable architectures design methodology Throughput Digital signal processing Parallel processing

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Equalizing data-path for processing speed determination in block level pipelining

Equalizing data-path for processing speed determination in b...

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IEEE International Symposium on Circuits and systems (ISCAS)

作者： Xiaoyao Liang A. Athalye Sangjin Hong Mobile Systems Design Laboratory Department of Electrical and Computer Engineering Stony Brook University-SUNY Stony Brook NY USA

Signal processing algorithms represented by data flow graphs can be efficiently mapped to hardware using a block level pipelining architecture. In this scheme, nodes of data flow are mapped to processing blocks and buffers are inserted in between as pipelining elements. We present, in this paper, a methodology for equalizing execution times of various nodes in the data path. The method is used to minimize the power dissipation and buffer usage by judiciously selecting the execution speed of hardware units. The block level pipelining allows for simple local controllers for each buffer which are generated by the global controller based on data flow specifications. The evaluation of the methodology on a practical example is presented.

关键词： Pipeline processing Communication system control Signal processing algorithms Control systems Hardware Centralized control Frequency synchronization Distributed control mobile computing Laboratories

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Glitching power reduction through supply voltage adaptation mechanism for low power array structure design

Glitching power reduction through supply voltage adaptation ...

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IEEE International Symposium on Circuits and systems (ISCAS)

作者： Sangjin Hong Shu-Shin Chin M. Sadasivam Mobile Systems Design Laboratory Department of Electrical and Computer Engineering Stony Brook University-SUNY Stony Brook NY USA

A novel supply voltage switching mechanism for reducing power dissipation of array structures is presented. With this mechanism, the supply voltage levels are successively activated by external clock signal in the direction of signal propagation. The mechanism eliminates power dissipated by the glitches while the speed of the array structure can be maintained. The mechanism is easily incorporated so that no circuit change in the existing array structure is required.

关键词： Power supplies Voltage Adaptive arrays Logic Switches Power dissipation Pipelines Registers Delay Clocks

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VLSI design of high-throughput processing element for real-time particle filtering

VLSI design of high-throughput processing element for real-t...

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International Symposium on Signals, Circuits and systems, SCS 2003

作者： Chin, Shu-Shin Hong, Sangjin Mobile Systems Design Laboratory Department of Electrical and Computer Engineering State University of New York at Stony Brook Stony BrookNY11794-2350 United States

ISBN: (纸本)0780379799

This paper presents a VLSI ASIC design of a high-throughput processing element for real-time particle filtering applications. The implementation is based on robust and efficient fixed-point processing algorithms. The high-throughput is achieved through two-level pipelining and preserving the inherent parallelism. The pipeline depth is balanced among sub-units to reduce clock loading via reduction of unnecessary registers. The processing element can be used as a standalone particle filter or a part of parallel particle filters for high-speed and/or larger particles. © 2003 IEEE.

关键词： Monte Carlo methods

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