In this paper a dual-port 512 Kb SRAM macro with hybrid dual power supply design is *** memory implemented using a dual port memory core,which is combined with a novel read delta-volt enhancement circuit to decrease i...
详细信息
In this paper a dual-port 512 Kb SRAM macro with hybrid dual power supply design is *** memory implemented using a dual port memory core,which is combined with a novel read delta-volt enhancement circuit to decrease its VDDmin and thus the additional power saving can be achieved.A test-chip has been fabricated in UMC 40 nm logic low-power and low-K *** macro can markedly save 26% dynamic power compared to conventional same density dual-port SRAM instance and only 4.5% area overhead.
In this paper a highly flexible low power single port Static Random Access Memory (SRAM) compiler design is *** Divided Word Line (DWL) and Divided Bit Line (DBL) scheme were implemented for reducing active *** emphas...
详细信息
In this paper a highly flexible low power single port Static Random Access Memory (SRAM) compiler design is *** Divided Word Line (DWL) and Divided Bit Line (DBL) scheme were implemented for reducing active *** emphasis was put to decrease standby power consumption in word line *** forced-stack devices as pulse generation element was introduced for sensing *** guarantees SRAM can work in low voltage without losing design margin.A test-chip with 17 embedded SRAMs has been fabricated in UMC 90-nm low leakage CMOS logic process.
In this paper a highly flexible low power single port Static Random Access Memory (SRAM) compiler design is presented. The Divided Word Line (DWL) and Divided Bit Line (DBL) scheme were implemented for reducing active...
详细信息
In this paper a highly flexible low power single port Static Random Access Memory (SRAM) compiler design is presented. The Divided Word Line (DWL) and Divided Bit Line (DBL) scheme were implemented for reducing active power. Particular emphasis was put to decrease standby power consumption in word line driver. The forced-stack devices as pulse generation element was introduced for sensing enable. This guarantees SRAM can work in low voltage without losing design margin. A test-chip with 17 embedded SRAMs has been fabricated in UMC 90-nm low leakage CMOS logic process.
暂无评论