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Substrate bias effects in p-channel GaN-on-Si transistors

Science China(Information Sciences) 2025年第1期68卷 404-405页

作者： Mengyao ZHAO Jie MA Lanlan YANG Chuanqi PAN Denggui WANG Jianjun ZHOU Sheng LI Jiaxing WEI Long ZHANG Siyang LIU Weifeng SUN National ASIC System Engineering Research Center School of Integrated Circuits Southeast University National Center of Technology Innovation for Electronic Design Automation Southeast University National Key Laboratory of Solid-State Microwave Devices and Circuits

The drain current （ID） of the n-channel GaN field-effecttransistor （n-FET） is influenced by the substrate-to-source bias voltage (VBS)（substrate bias effect）[1].Actually,nonzero VBSis also likely to occur in p-FET in real application,because the source electrode of p-FET is usually connected to high *** study reports the dependency between IDand VBSin p-FET for the first time,and analyzes the underlying mechanisms from the perspective of vertical electric field （EF） distribution.

关键词： bias effects p-channel substrate transistors

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Variation-Aware Clock Path Timing Model in Near-Threshold Voltage

Variation-Aware Clock Path Timing Model in Near-Threshold Vo...

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2023 International Symposium of Electronics Design Automation, ISEDA 2023

作者： Liu, Long-Ji Zhang, Hao Wang, Xue-Xiang National ASIC System Engineering Technology Research Center Southeast University Nanjing China

ISBN: (纸本)9798350304510

A clock path timing modeling method for near-Threshold voltage circuits is adopted in this paper, which is composed of clock cell models and interconnect models using regression fitting methods. The proposed near-Threshold clock tree timing modeling methods are validated on the ISCAS89 benchmark circuits and the Cortex-M3 benchmark circuit with the SMIC40LL process. The results show that compared with the clock tree obtained by the EDA tool (IC Compiler), the method proposed in this thesis reduces the clock skew by 35.1% on average and the clock skew variation (standard deviation of clock skew) by 37.3% on average. © 2023 IEEE.

关键词： Timing circuits

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Multiple-Input Switching Modeling with Graph Neural Network

Multiple-Input Switching Modeling with Graph Neural Network

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2023 International Symposium of Electronics Design Automation, ISEDA 2023

作者： Jiang, Haiyang Cheng, Xu Cao, Peng Southeast University National ASIC System Engineering Technology Research Center Nanjing China

ISBN: (纸本)9798350304510

Multiple Input Switching (MIS) poses great challenge in Static Timing Analysis (STA) with unexpected setup or hold violations due to temporal proximity among transitions at different inputs of gate. Most prior empirical and learning based models are ad hoc techniques which should be applied to each gate separately and ignore the relation of MIS with transistor-level gate topology, leading to poor estimation accuracy and/or considerable characterization effort. In this work, a Graph Neural Network (GNN) based model is proposed to predict MIS-SIS Difference (MSD), which is trained jointly as a unified model by mapping transistor-level gate topology into nodes and edges of graph. The proposed model was validated under TSMC 16nm process for a set of multiple-input gates and paths from ISCAS'85 and TAU benchmarks. Experimental results demonstrate excellent agreement with golden SPICE simulation results by this work with NRMSE error less than 0.73% in average for all validated gates. Comparing with prior learning based approach, our model achieves 2.7× characterization effort reduction with comparative accuracy. The predicted path delays with MIS effect with our model is highly consistent to SPICE simulation results with the average error 2.0%. © 2023 IEEE.

关键词： Topology

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An Improved Quadrangle Control Strategy for Four-Switch Buck-Boost Converters With Load Current Feedforward

An Improved Quadrangle Control Strategy for Four-Switch Buck...

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Energy, Electrical and Power engineering (CEEPE), International Conference on

作者： Xiangxiang Wang Qi Liu Wei Liu Luxiao Yuan Siyang Liu Qinsong Qian Weifeng Sun Nation ASIC System Engineering & Research Center Southeast University Nanjing China

ISBN: (数字)9798331521844

ISBN: (纸本)9798331521851

The insufficient dynamic response of Four-Switch Buck-Boost (FSBB) converters in 48V data center power systems is addressed in this study through the proposal of a load current feedforward dynamic control strategy. A small-signal model of the FSBB converter is established, and a voltage single-loop control architecture without current inner loops is designed. Compensation is achieved through the direct injection of load current derivative signals, resulting in a significant enhancement of control bandwidth. Simulation results demonstrate that, at a switching frequency of 500 kHz, the transient response time during load step changes is reduced by 33% compared to conventional PI control, while output voltage variation is decreased by more than 50%. The effectiveness of the proposed methodology is thereby validated.

关键词： Dynamic response Transient response Voltage fluctuations Switching frequency Power system dynamics Time factors Voltage control Transient analysis Feedforward systems Load modeling

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A High Power Density Coupled Inductor Design for Multi-phase Buck Converters

A High Power Density Coupled Inductor Design for Multi-phase...

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Energy, Electrical and Power engineering (CEEPE), International Conference on

作者： Wei Liu Qi Liu Xiangxiang Wang Luxiao Yuan Wangran Wu Qinsong Qian Weifeng Sun Nation ASIC System Engineering & Research Center Southeast University Nanjing China

ISBN: (数字)9798331521844

ISBN: (纸本)9798331521851

With the increasing demand for miniaturization and high efficiency in modern electronic devices, particularly in 48V architecture server power supplies, the 2N-phase Buck converter has garnered significant attention due to its ability to achieve efficient conversion from 48V to 1V at high duty cycles. This paper proposes a miniaturized inductor design method suitable for coupled-inductor Buck converters, aiming to address the limitations of traditional inductors in meeting the requirements of high power density and efficiency. By modeling to determine the optimal coupling coefficient, the effective value of the inductor current is significantly reduced, thereby minimizing circuit ripple and losses. Building on this, a method for optimizing the core size and winding turns is designed, effectively improving conversion efficiency and reducing component volume. Simulation verification using Maxwell software confirms that the magnetic flux density and current density distributions align with the design expectations, validating the accuracy and reliability of the proposed method. The research results demonstrate that the proposed design method significantly enhances the performance of coupled inductors in high-efficiency, miniaturized power converters, providing theoretical support and practical guidance for further optimization and application in related fields.

关键词： Power system measurements Magnetic flux density Buck converters Density measurement Design methodology Magnetic cores Windings Power electronics Inductors Optimization

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A Statistical Evaluation Method to Quantify the Runtime Uncertainty of Accelerator-rich SoC Targeting EDA Acceleration

A Statistical Evaluation Method to Quantify the Runtime Unce...

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2023 International Symposium of Electronics Design Automation, ISEDA 2023

作者： Huang, Shuaibo Shi, Longxing Southeast University National ASIC System Engineering Technology Research Center Jiangsu Nanjing China

ISBN: (纸本)9798350304510

Integrating a host CPU with domain-specific accelerators is a promising way to improve the performance/power/area of EDA acceleration in the post-Moore age. But it is hard to estimate the runtime performance of the accelerator-rich SoC in the early stage, especially considering the uncertainty produced by PVT variation. To predict and further avoid the architectural risk, we propose a statistical model to evaluate the runtime distribution while targeting EDA acceleration. We first collect the dataset by the Latin hypercube sampling method and dump the output runtime data via gem5-SALAM simulator. After transforming the original dataset into the Gauss distribution through box-cox transformation, we integrate the least square boosting regression to achieve the deterministic estimation. Then we inject the uncertainties of frequency and unit yield, and thus the predictions become distributions. Based on the statistical evaluation method with a 4.3% normalized MSE, we can find that the experimental performance is usually worse than the original deterministic estimation, which proves the architectural risk. © 2023 IEEE.

关键词： system-on-chip

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A Dual-Channel Four-Switch Resonant Gate Driver for LLC Secondary Side MOSFETs

A Dual-Channel Four-Switch Resonant Gate Driver for LLC Seco...

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Power systems and Electrical technology (PSET), IEEE International Conference on

作者： Ziyan Zhou Qiang Luo Yufan Wang Yuefei Sun Qinsong Qian Weifeng Sun Nation ASIC System Engineering & Research Center Southeast University Nanjing China

ISBN: (数字)9798350353204

ISBN: (纸本)9798350353211

Due to its superior soft-switching characteristics, the LLC resonant converter achieves efficient power transmission at high frequencies and is extensively utilized in high power density applications. Conventional drivers exhibit loss that increase proportionally with frequency, resulting in excessive driving loss at high frequencies. To address this, a dual-channel four-switch resonant gate driver (DCFSRGD) is introduced in this paper to drive the secondary-side MOSFETs of the LLC. The proposed DCFSRGD can adjust duty cycles and switching frequencies through appropriate control timing, achieving 82% energy recovery compared to conventional drivers. Unlike other resonant gate drivers used in LLC-DCX applications, this DCFSRGD also facilitates changes in duty cycle and frequency, making it suitable for variable frequency LLC applications. This paper details the operational principles and optimized design methods of the proposed driver. A prototype with a resonant frequency of 1.3 MHz was constructed to validate the effectiveness of the proposed resonant gate driver.

关键词： MOSFET Switching frequency Resonant frequency Resonant converters Gate drivers Frequency conversion Control systems Timing High frequency Voltage control

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A Power Supply and High-Voltage Blocking Sensing Circuit for High Voltage Synchronous Rectifier

A Power Supply and High-Voltage Blocking Sensing Circuit for...

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Annual IEEE Conference on Applied Power Electronics Conference and Exposition (APEC)

作者： Song Ding Chunyan Nie Minggang Chen Ziyan Zhou Lanxin Gu Qinsong Qian Nation ASIC System Engineering & Research Center Southeast University Nanjing China

Commercial synchronous rectifier (SR) ICs usually have a limited V DS (drain-source voltage) rating of about 200V, which will restrict their applications in high-voltage SR circuits. This paper proposes a novel power supply and high-voltage blocking sensing circuit for high voltage SRs, which is improved on the basis of traditional transistor series voltage regulator power supply circuits and realizes the high-voltage blocking of the detected high V DS without sacrificing the detection accuracy. Meanwhile, the proposed circuit has low cost and high versatility, and can be applied to existing commercial SR control ICs, which greatly reduces the input sense voltage of the SR controller on the one hand, and supplies power for SR IC on the other. Finally, the proposed power supply and high-voltage blocking sensing circuit is verified on a 720kHz flyback converter with ON Semiconductor's NCP4306 SR control IC.

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A novel high-frequency isolated resonant gate driver for LLC-DCX

A novel high-frequency isolated resonant gate driver for LLC...

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Annual IEEE Conference on Applied Power Electronics Conference and Exposition (APEC)

作者： Ziyan Zhou Qiang Luo Yuefei Sun Yufan Wang Qinsong Qian Weifeng Sun Nation ASIC System Engineering & Research Center Southeast University Nanjing China

The fixed-frequency unregulated LLC DC transformer (DCX) operates at MHz switching frequency, leading to high efficiency and high-power density. However, at this frequency, the LLC-DCX experiences substantial gate drive losses. To address this issue and achieve gate drive energy recovery, a new zero-voltage-switching high-frequency isolated resonant gate driver (RGD) for the LLC-DCX is proposed. The proposed RGD is capable of providing the drive signals for all MOSFETs in the LLC-DCX, resulting in an 85.5% reduction in drive losses compared to conventional drivers. The paper provides a detailed analysis of the operating principle, key parameter L rd design, and loss analysis of the proposed RGD. Finally, a prototype that operates at 1.3MHz is constructed to validate the effectiveness of the proposed circuit.

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An Accurate Statistical Cell Delay Model Considering Multiple-Input Switching Effect

An Accurate Statistical Cell Delay Model Considering Multipl...

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2023 International Symposium of Electronics Design Automation, ISEDA 2023

作者： Xu, Jiajie Jin, Leilei Yan, Hao School of Electronic Science and Engineering Southeast University Nanjing210096 China The National ASIC System Engineering Technology Research Center China

ISBN: (纸本)9798350304510

To restrict the storage overhead, traditional statistical static timing analysis (SSTA) employs a delay model that assumes only a single input switches for a cell during a transition, while all other side inputs are held constant. Nevertheless, ignoring the impact of multiple-input switching (MIS) can lead to an overestimation or an underestimation of a cell delay, causing over-designing for the timing margin. In this paper, we present a novel approach using expected scale factors to assess the impact of MIS on statistical timing analysis. Meanwhile, an accurate cell delay calibration method considering skewness and kurtosis is proposed to measure the 30σ cell delay. Tested by cells with TSMC 28nm technology, our model can estimate the 3σ point with similar accuracy comparing to state-of-the-art technology in single-input switching (SIS) mode. Moreover, in near-/sub-threshold voltage, the cell delay computed by our model in MIS mode differs from the SPICE-computed delay by less than 4%, which infers significant improvement over MIS delay models proposed by prior studies. © 2023 IEEE.

关键词： Cells

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