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Substrate bias effects in p-channel GaN-on-Si transistors

Science China(Information Sciences) 2025年第1期68卷 404-405页

作者： Mengyao ZHAO Jie MA Lanlan YANG Chuanqi PAN Denggui WANG Jianjun ZHOU Sheng LI Jiaxing WEI Long ZHANG Siyang LIU Weifeng SUN National ASIC System Engineering Research Center School of Integrated Circuits Southeast University National Center of Technology Innovation for Electronic Design Automation Southeast University National Key Laboratory of Solid-State Microwave Devices and Circuits

The drain current （ID） of the n-channel GaN field-effecttransistor （n-FET） is influenced by the substrate-to-source bias voltage (VBS)（substrate bias effect）[1].Actually,nonzero VBSis also likely to occur in p-FET in real application,because the source electrode of p-FET is usually connected to high *** study reports the dependency between IDand VBSin p-FET for the first time,and analyzes the underlying mechanisms from the perspective of vertical electric field （EF） distribution.

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LAG-Sizer: A Novel Gate Sizer Based on Leak Generative Adversarial Network with Feature Fusion 24

LAG-Sizer: A Novel Gate Sizer Based on Leak Generative Adver...

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43rd International Conference on Computer-Aided Design, ICCAD 2024

作者： Zhang, Zhanhua Ding, Wenjing He, Guoqing Cao, Peng National ASIC System Engineering Technology Research Center Southeast University Nanjing China National Center of Technology Innovation for EDA Nanjing China

ISBN: (纸本)9798400710773

Gate sizing is an NP-hard problem to achieve Performance, Power and Area (PPA) optimization. Recently proposed learning-based approaches struggle to overcome the runtime issue of traditional heuristics, but lack the consideration of the intrinsic features for candidate gates in library and could not address the inequality issue of candidate sizes for different gates properly, suffering from insufficient design space exploration and inaccurate sizing assignment. In this work, based on a variant of generative adversarial network, Leak Adversarial Generation (LAG), a novel LAG-Sizer is proposed to model gate sizing as sequence generation problem, which breaks the traditional adversarial network by leaking the discriminator feature information into the generator to guide sizing generation. Feature fusion technique is introduced to comprehensively consider circuit feature and cell library feature while a unified classification is proposed to perfectly solve the inequality issue for sizing. The proposed sizer was validated with IWLS2005 and Opencores benchmark circuits under 22nm process. Experimental results demonstrate that an average of 4.6% Total Negative Slack (TNS) improvement and 15.6% number of violating endpoints (NVE) reduction are achieved by this work with similar area and power consumption compared to commercial tools as well as significant runtime speedup of 47.8×. © 2024 Copyright is held by the owner/author(s).

关键词： Generative adversarial networks

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A Physical and Timing Aware Placement Optimization Framework Based on Graph Neural Network 24

A Physical and Timing Aware Placement Optimization Framework...

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43rd International Conference on Computer-Aided Design, ICCAD 2024

作者： Ding, Wenjie Zhang, Zhanhua He, Guoqing Cao, Peng National ASIC System Engineering Technology Research Center Southeast University Nanjing China National Center of Technology Innovation for EDA Nanjing China

ISBN: (纸本)9798400710773

Timing-driven placement is crucial in physical design flow with significant impact on later routability and ultimate manufacturability, which may deviate from finding the optimal solution and/or lead to unnecessary iterations, suffering from interleaved optimization steps and the corresponding inaccurate timing estimation. To solve this issue, we propose a Physical and Timing Aware framework with Graph Neural Network, PTA-GNN, which provides the candidate gate sizing and buffer insertion solutions as well as the timing constraint for potential violated paths as guidance to improve placement quality significantly. Experimental results on the OpenCores benchmarks with 22nm technology demonstrate that the proposed placement optimization framework achieves up to 89.09% worst negative slack (WNS), 55.47% total negative slack (TNS) improvement and 25.36% reduction on the number of violating paths (#VP). Our framework benefits the later routing stage with 2.19% wirelength decrease and 22% runtime reduction compared to standard physical design flow. © 2024 Copyright is held by the owner/author(s).

关键词： Graph neural networks

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RE-SEGNN:recurrent semantic evidence-aware graph neural network for temporal knowledge graph forecasting

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Science China(Information Sciences) 2025年第2期68卷 103-119页

作者： Wenyu CAI Mengfan LI Xuanhua SHI Yuanxin FAN Quntao ZHU Hai JIN National Engineering Research Center for Big Data Technology and System Services Computing Technology and System LabCluster and Grid Computing LabSchool of Computer Science and TechnologyHuazhong University of Science and Technology

Temporal knowledge graph(TKG) reasoning, has seen widespread use for modeling real-world events, particularly in extrapolation settings. Nevertheless, most previous studies are embedded models, which require both entity and relation embedding to make predictions, ignoring the semantic correlations among different entities and relations within the same timestamp. This can lead to random and nonsensical predictions when unseen entities or relations occur. Furthermore, many existing models exhibit limitations in handling highly correlated historical facts with extensive temporal depth. They often either overlook such facts or overly accentuate the relationships between recurring past occurrences and their current counterparts. Due to the dynamic nature of TKG, effectively capturing the evolving semantics between different timestamps can be *** address these shortcomings, we propose the recurrent semantic evidenceaware graph neural network(RE-SEGNN), a novel graph neural network that can learn the semantics of entities and relations simultaneously. For the former challenge, our model can predict a possible answer to missing quadruples based on semantics when facing unseen entities or relations. For the latter problem, based on an obvious established force, both the recency and frequency of semantic history tend to confer a higher reference value for the current. We use the Hawkes process to compute the semantic trend, which allows the semantics of recent facts to gain more attention than those of distant facts. Experimental results show that RE-SEGNN outperforms all SOTA models in entity prediction on 6 widely used datasets, and 5 datasets in relation prediction. Furthermore, the case study shows how our model can deal with unseen entities and relations.

关键词： knowledge graph reasoning temporal knowledge graph Hawkes process semantic evidence

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Spiking Reinforcement Learning Enhanced by Bioinspired Event Source of Multi-dendrite Spiking Neuron and Dynamic Thresholds

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IEEE/CAA Journal of Automatica Sinica 2025年第3期12卷 618-629页

作者： Xingyue Liang Qiaoyun Wu Yun Zhou Chunyu Tan Hongfu Yin Changyin Sun the School of Artificial Intelligence Anhui University Engineering Research Center of Autonomous Unmanned System Technology Ministry of Education IEEE the Institute of Artificial Intelligence Hefei Comprehensive National Science Center the School of Automation Southeast University the Engineering Research Center of Autonomous Unmanned System Technology Ministry of Education

Deep reinforcement learning(DRL) achieves success through the representational capabilities of deep neural networks(DNNs). Compared to DNNs, spiking neural networks(SNNs),known for their binary spike information processing, exhibit more biological characteristics. However, the challenge of using SNNs to simulate more biologically characteristic neuronal dynamics to optimize decision-making tasks remains, directly related to the information integration and transmission in *** by the advanced computational power of dendrites in biological neurons, we propose a multi-dendrite spiking neuron(MDSN) model based on Multi-compartment spiking neurons(MCN), expanding dendrite types from two to multiple and deriving the analytical solution of somatic membrane *** apply the MDSN to deep distributional reinforcement learning to enhance its performance in executing complex decisionmaking tasks. The proposed model can effectively and adaptively integrate and transmit meaningful information from different sources. Our model uses a bioinspired event-enhanced dendrite structure to emphasize features. Meanwhile, by utilizing dynamic membrane potential thresholds, it adaptively maintains the homeostasis of MDSN. Extensive experiments on Atari games show that the proposed model outperforms some state-of-the-art spiking distributional RL models by a significant margin.

关键词： Deep reinforcement learning multi-compartment spiking neurons spiking neural network

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Two Compact Hybrid Band-Pass Filters Using Eighth-Mode Substrate-Integrated Waveguide and Microstrip Resonators

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Progress in Electromagnetics research C 2025年 151卷 167-175页

作者： Tang, Luyao Han, Wei Wei, Hao Li, Yanbin The 54th Research Institute of China Electronics Technology Group Corporation China National Engineering Reasearch Center of Communication Software and Asic Design China

Two compact substrate-integrated waveguide (SIW) filters with hybrid coupling of eighth-mode substrate integrated waveg-uide (EMSIW) resonators and microstrip are proposed in this paper. Hybrid coupled filters were achieved by etching two half-wavelength microstrip resonators (BPF I) or two quarter-wavelength microstrip resonators (BPF II) on the top of traditional second-order EMSIW filters. The topology of the two filters was analyzed. Due to the cross coupling between resonator 1 and resonator 4, two transmission zeros were achieved outside the band of BPF I, which increased the selectivity of the filter. Due to the mixed electromagnetic coupling between resonator 2 and resonator 3, a transmission zero is realized in the stopband of BPF II. To confirm the validity of the two filter models, two filters were designed, produced, and measured. Based on the findings of the measurements, the central frequency of BPF I is recorded at 7.7 GHz, with a fractional bandwidth (FBW) of 18.2%. The insertion loss (IL) within the passband is minimal at 0.8 dB, and the size of the filter is only 8 mm * 4 mm (0.53λg *0.26λg). The filter exhibits enhanced out-of-band suppression due to the presence of two transmission zeros located at frequencies of 6.4 GHz and 10 GHz. The center frequency of BPF II is 19.5 GHz,; the FBW is 20.5%; the IL within the passband is only 0.49 dB; and the size of the filter is only 2 mm ∗ 2 mm (0.34λg *0.34λg). As a result of the mixed electromagnetic coupling effects, a transmission zero occurs at a frequency of 26.7 GHz. The simulation outcomes are consistent with the experimental findings. Compared with other reported SIW filters, the two filters introduced in this study exhibit favorable characteristics such as reduced insertion loss and compact dimensions. © 2025, Electromagnetics Academy. All rights reserved.

关键词： Bandpass filters

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High Efficiency High Power Density Double-Clamp ZVS Flyback Converter with Secondary Absorption

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IEEE Transactions on Power Electronics 2025年

作者： Ding, Song Chen, Li Qian, Qinsong Sun, Weifeng Southeast University National ASIC System Engineering Research Center Nanjing China

The double-clamp zero-voltage-switching (DCZVS) flyback converter can achieve high efficiency and high power density through high frequency soft switching and inherent primary side regulation (PSR) feature. However, conventional resonance schemes for DCZVS flyback converters fail to simultaneously enable lossless leakage inductance energy recovery and high-precision PSR. In this article, a secondary absorption scheme is proposed for the DCZVS flyback converter, which employs the output capacitance of secondary-side synchronous rectifier (SR) switch to achieve lossless absorption of leakage inductance energy. Furthermore, the secondary absorption scheme reduces the voltage ripple of the clamp voltage and enhances PSR accuracy. The proposed scheme is validated on a 160-420V input and 28V/600W output prototype. Compared with the highest power density level at present, the experimental prototype achieves a peak efficiency of 94.37% with an increase of 0.68%, and achieves an ultra-high power density of 1290 W/inch3 with an increase of 7.2%. © 1986-2012 IEEE.

关键词： Double-clamp zero-voltage-switching (DCZVS) flyback converter high efficiency high power density primary side regulation secondary absorption

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An Ultra Low Steady-State Current Power-on-Reset Circuit in 65nm CMOS technology

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Chinese Journal of Electronics 2025年第4期23卷 678-681页

作者： Weiwei Shan Xuexiang Wang Xinning Liu Huafang Sun National ASIC System Engineering Research Center Southeast University Nanjing China

A novel Power-on-reset (POR) circuit is proposed with ultra-low steady-state current consumption. A band-gap voltage comparator is used to generate a stable pull-up voltage. To eliminate the large current consumptions of the analog part, a power switch is adopted to cut the supply of band-gap voltage comparator, which gained ultra-low current consumption in steady-state after the POR rest process completed. The state of POR circuit is maintained through a state latch circuit. The whole circuit was designed and implemented in 65nm CMOS technology with an active area of 120μm*160μm. Experimental results show that it has a steady pull-up voltage of 0.69V and a brown-out voltage of 0.49V under a 1.2V supply voltage rising from 0V, plus its steady-state current is only 9nA. The proposed circuit is suitable to be integrated in system on chip to provide a reliable POR signal.

关键词： Latches Power demand Photonic band gap Voltage Switches Very large scale integration Logic gates CMOS technology Steady-state system-on-chip

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Soft-GNN:towards robust graph neural networks via self-adaptive data utilization

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Frontiers of Computer Science 2025年第4期19卷 1-12页

作者： Yao WU Hong HUANG Yu SONG Hai JIN National Engineering Research Center for Big Data Technology and System Service Computing Technology and System LabCluster and Grid Computing LabSchool of Computer Science and TechnologyHuazhong University of Science and TechnologyWuhan 430074China College of Information and Communication National University of Defense TechnologyWuhan 430019China Department of Computer Science and Operations Research Universitéde MontréalMontreal H3C 3J7Canada

Graph neural networks(GNNs)have gained traction and have been applied to various graph-based data analysis tasks due to their high ***,a major concern is their robustness,particularly when faced with graph data that has been deliberately or accidentally polluted with *** presents a challenge in learning robust GNNs under noisy *** address this issue,we propose a novel framework called Soft-GNN,which mitigates the influence of label noise by adapting the data utilized in *** approach employs a dynamic data utilization strategy that estimates adaptive weights based on prediction deviation,local deviation,and global *** better utilizing significant training samples and reducing the impact of label noise through dynamic data selection,GNNs are trained to be more *** evaluate the performance,robustness,generality,and complexity of our model on five real-world datasets,and our experimental results demonstrate the superiority of our approach over existing methods.

关键词： graph neural networks node classification label noise robustness

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Cost-Effective Edge Data Caching with Failure Tolerance and Popularity Awareness

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IEEE Transactions on Mobile Computing 2025年第6期24卷 5357-5369页

作者： Luo, Ruikun Zhang, Zujia He, Qiang Xu, Mengxi Chen, Feifei Dai, Xiaohai Wu, Song Jin, Hai Huazhong University of Science and Technology National Engineering Research Center for Big Data Technology and System Services Computing Technology and System Lab Cluster and Grid Computing Lab School of Computer Science and Technology China Deakin University School of Information Technology GeelongVIC3125 Australia

In the mobile edge computing environment, caching data in edge storage systems can significantly reduce data retrieval latency for users while saving the costs incurred by cloud-edge data transmissions for app vendors. Existing edge data caching (EDC) methods prioritize popular data and aim to minimize users' data retrieval latency and system storage costs jointly. However, these EDC methods often rely on the assumption that data popularity always follows certain distributions. As a result, they cannot properly adapt to the fluctuations in data popularity due to user mobility or unexpected increases in user demands. Meanwhile, unlike cloud data centers, complex and fragile edge servers are more likely to experience physical failures or network outages, presenting new challenges for EDC strategies. Specifically, when an edge server fails or experiences an outage, cached data may become temporarily unavailable, leading to increased latency as requests are redirected to alternative servers or the cloud. In this paper, to enable uncertainty-aware edge data caching (uEDC), we first model the problem as a robust optimization problem and propose an optimal algorithm named uEDC-B to find the optimal uEDC solution. To address the high computational complexity of uEDC-B, we introduce an approximate algorithm named uEDC-L based on linear decision rules. Theoretical analysis and extensive experiments on a real-world dataset demonstrate that the proposed methods outperform two state-of-the-art approaches in handling the uncertainties in data popularity and edge server failure with a significant performance improvement of 59.27% in data retrieval latency and 55.07% in data caching cost. © 2002-2012 IEEE.

关键词： Mobile edge computing

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