A memory architecture is proposed to automatically explore the design space consisting of data reuse for sliding window applications, in the context of FPGAtargeted hardware compilation. Sliding window operator is wid...
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ISBN:
(纸本)9781424458219;9781424458240
A memory architecture is proposed to automatically explore the design space consisting of data reuse for sliding window applications, in the context of FPGAtargeted hardware compilation. Sliding window operator is widely used in the typical applications on reconfigurable system, such as image processing, pattern recognition anddigital signal processing, etc. But the sliding window circuit generated by reconfigurable compilersystem is not so efficiency, limited by redundant storage, waiting operation and so on. In this paper, we present a block-based storage data reuse method to increases data throughput in sliding window applications. Through parallel access the window data, our method can reduce memory access time and improve the performance of hardware circuit. Experiments show that in three typical applications of sliding window, this approach can achieve accelerating of sliding window circuit, the performance of the program enhances 6.5-7.9 times.
Lack of preventive measures against junk fax is a great problem in the research on fax server. Safety fax server is proposed in this paper, which detect the received fax before distributing them in order to prevent us...
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Lack of preventive measures against junk fax is a great problem in the research on fax server. Safety fax server is proposed in this paper, which detect the received fax before distributing them in order to prevent users from junk fax. Because junk faxes spread in the form of broadcast, the server carries on preliminary flitting by clustering the incoming fax at first, and then uses Optical Characterrecognition (OCr) technology to recognize the keywords anddistinguish the junk fax. Proved by experiment, this method is not only easy to implement, but also available.
Managing and searching facsimiles automatically is the key point to achieve OA (Office Automation). At present, there is a lack of method to establish index of fax, which is the basis of searches. Focus on official bu...
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Managing and searching facsimiles automatically is the key point to achieve OA (Office Automation). At present, there is a lack of method to establish index of fax, which is the basis of searches. Focus on official business faxes, this paper proposes an approach to create index of fax, using logo, stamp and keywords, after analyzing the characteristics of these faxes thoroughly. The result illuminates that this method can improve the robustness to noise efficiently, and obtains high performance in Precision andrecall.
To address the problem of IO process machine virtualization resulting tight coupling, scheduling delays in virtual machine monitor with hybrid model, a cooperative virtual machine monitor proposed, which uses hardware...
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ISBN:
(纸本)9781424458219;9781424458240
To address the problem of IO process machine virtualization resulting tight coupling, scheduling delays in virtual machine monitor with hybrid model, a cooperative virtual machine monitor proposed, which uses hardware partition for IO process machine to operate independently, eliminates tight coupling between IO process machine and virtual machine monitor, and avoids asynchronous problems caused by IO process machine involved in scheduling. This model can be extended to multiple parallel IO process machines to achieve load balancing and failure replacement. Implementation and test show that the structure of the virtual machine monitor is able to improve IO performance, and is a viable virtualization scheme.
Aiming at the problem of data transfer for virtualmachine monitor in device access, a communications mode in double systems based on multi-core processor is proposed. Two key problem in this mode buffer overflow and p...
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ISBN:
(纸本)9781424458219;9781424458240
Aiming at the problem of data transfer for virtualmachine monitor in device access, a communications mode in double systems based on multi-core processor is proposed. Two key problem in this mode buffer overflow and package pseudo loss are analyzed, communications mechanism based on Inter-processor interrupts and shared memory is constructed, data transfer between virtual-machine monitor and IO process machine is implemented. Efficiency of communications is enhanced by IPI multiplex, cache customization ect. Finally, guide line of communications such as arrival ratio, transferratio of package, system load is tested and conclusion is presented. Experimental results showed that the communications mode in double systems based on multicore processor could provide communications platform with stabilization and high efficiency.
Multiple-session Sod problem is addressed in the static constraint rBAC model. An improved formal static constraint rBAC model is proposed and it will check the change of the VA relation to decide whether the union of...
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Multiple-session Sod problem is addressed in the static constraint rBAC model. An improved formal static constraint rBAC model is proposed and it will check the change of the VA relation to decide whether the union of the user's role set will satisfy the MEr constraint during an administrative session. If it will not satisfy the constraint, some necessary withdrawing will be performed. The improved model conserves the advantage of the MEr mechanism and handles multiple-session Sod problem efficiently.
Taking account of defections existed in general methods of implementing IP security (IPsec) in broadbandrouters, a secure scheme based on fast path and slow path of routers was put forward. The scheme implements IPse...
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Taking account of defections existed in general methods of implementing IP security (IPsec) in broadbandrouters, a secure scheme based on fast path and slow path of routers was put forward. The scheme implements IPsec with Encryption chip and IPsec software combined, and adopts Encryption adaptive board to support multi-encryption chips. No requirement for change in original hardware architecture of broadbandrouter makes the scheme universal. Wire-speeddata forwarding and encryption are processed in fast path, while local data and protocol data which are non-real time tasks are processed in slow path, in which IPsec security policy (SP) and security association (SA) are also transferred. The scheme was tested in Sr1880s, and testing results showed that the proposed scheme can satisfy the security needs of broadbandrouter.
Separation of identifier and locator provides good conditions of routing scalability and mobility for Internet routing and lP addressing. Based on the idea of identifier and locator separation, in this paper we i...
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Separation of identifier and locator provides good conditions of routing scalability and mobility for Internet routing and lP addressing. Based on the idea of identifier and locator separation, in this paper we introduce the access identifier (AId) and the routing locator (rLOC), design a network locality-aware distributed hash table (NLAdHT), then present an identifier mapping information storage algorithm with network locality-aware capability (N3Chord). Simulation performance shows that, the identifiers of distributed network storage nodes assigned by NLA-dHT with good query performance in network topology locality consistency, and the query efficiency and network fault handling capability of N3-Chord is much superior to Chord FingerPNS and ChordFinger.
The current network-on-chip （NoC） topology cannot predict subsequent switch node status promptly. Switch nodes have to perform various functions such as routing decision, data forwarding, packet buffering, congestio...
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The current network-on-chip （NoC） topology cannot predict subsequent switch node status promptly. Switch nodes have to perform various functions such as routing decision, data forwarding, packet buffering, congestion control and properties of an NoC system. Therefore, these make switch architecture far more complex. This article puts forward a separating on-chip network architecture based on Mesh （S-Mesh）, S-Mesh is an on-chip network that separates routing decision flow from the switches. It consists of two types of networks： datapath network （dN） and control network （CN）. The CN establishes data paths fordata transferring in dN. Meanwhile, the CN also transfers instructions between different resources. This property makes switch architecture simple, and eliminates conflicts in network interface units between the resource and switch. Compared with 2d-Mesh, Toms Mesh, Fat-tree and Butterfly, the average packet latency in S-Mesh is the shortest when the packet length is more than 53 B. Compared with 2d-Mesh, the areas savings of S-Mesh is about 3%-7/% and the powerdissipation is decreased by approximate 2%.
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