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A performance study of CSMA in wireless networks with successive interference cancellation

A performance study of CSMA in wireless networks with succes...

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IEEE International Conference on Communications (ICC)

作者： Shaohe Lv Weihua Zhuang Xiaodong Wang Chi Liu Xiaofeng Hu Yipin Sun Xingming Zhou Institute of Network Information and Security National University of Defense Technology Changsha China Department of Electrical and Computer Engineering University of Waterloo Waterloo ONT Canada Central South University Changsha China National Laboratory of Parallel and Distributed Processing National University of Defense Technology Changsha China

Successive interference cancellation (SIC) is an effective way of multipacket reception to combat interference. As conventional CSMA (Carrier Sense Multiple Access) is designed for single packet reception, it is unclear whether or not CSMA performs well to exploit the SIC capability. In this paper, we analyze the performance of a simple CSMA protocol in a network with SIC. For a given link, we derive the residing areas of an interfering node when simultaneous transmission is allowed and when the interference is harmful, respectively. We show that, though SIC provides many new transmission opportunities, CSMA cannot effectively exploit them. There is a fundamental tradeoff in a CSMA protocol between exploiting the transmission opportunities from SIC and capturing the harmful interference. In many cases, when CSMA achieves its best performance, almost all new transmission opportunities are not exploited. It is therefore very necessary to design a new distributed access protocol in wireless networks with SIC.

关键词： Silicon carbide Multiaccess communication Interference Receivers Propagation losses Protocols Wireless networks

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Memory access characterization of scientific applications on GPU and its implication on low power optimization

Memory access characterization of scientific applications on...

引用

2011 International Conference on Computational and Information Sciences, ICCIS 2011

作者： Wang, Guibin National Laboratory for Parallel and Distributed Processing National University of Defense Technology China

ISBN: (纸本)9780769545011

Following current IC design technology trend, modern GPUs integrate more and more processing cores, and the speed gap between processor and memory system becomes even larger. As the number of cores continually increases, the available bandwidth per core decreases correspondingly. Therefore, memory access performance has been one of the most critical bottlenecks for better performance. This paper analyzes the impact of memory system on performance and scalability for GPU with several scientific applications using a cycle-accurate simulator. Two observations we make are (1) that memory bandwidth has relatively greater impact on performance than memory latency, because the latter factor could be well hidden with tremendous concurrent executing threads supported in modern GPU architecture, and (2) that through examining the performance scalability of variable active cores, using the maximum hardware-supported cores may not bring in better performance, especially for the memory-intensive applications. In the end we suggest a better power-efficient exploitation of GPU is to make judicious concurrency-throttling based on the memory usage in application. © 2011 IEEE.

关键词： Graphics processing unit

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Communication-aware task partition and voltage scaling for energy minimization on heterogeneous parallel systems

Communication-aware task partition and voltage scaling for e...

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2011 12th International Conference on parallel and distributed Computing, Applications and Technologies, PDCAT 2011

作者： Wang, Guibin Song, Wei National Laboratory for Parallel and Distributed Processing National University of Defense Technology China

ISBN: (纸本)9780769545646

Heterogeneous parallel systems have become popular in general purpose computing and even high performance computing fields. There are many studies focused on harnessing heterogeneous parallel processing for better performance. However the energy optimization for heterogeneous system has not been well studied. Owing to the differences in performance and energy consumption, the energy optimization technique for heterogeneous system is different from the existing methods designed for homogeneous system. Besides typical voltage scaling method, reasonable task partitioning is also an essential method for optimizing energy consumption on heterogeneous systems. Through partitioning a data parallel task and mapping sub-tasks onto several processors, one could achieve better performance and reduced energy consumption. As the computation cost reduces with specific accelerators, the communication overhead becomes more prominent. Therefore, the task partition optimization should holistically consider the computation improvement and communication overhead to achieve higher energy efficiency. Typically, task partition and voltage scaling are not orthogonal and influence the effect of each other in the energy optimization problem. In order to harness both two knobs efficiently, this paper proposes an integer linear programming (ILP) based energy-optimal solution designed for heterogeneous system. We present a case study of optimizing MGRID benchmark on a typical CPU-GPU heterogeneous system. The experimental results demonstrate that the proposed method could exploit the heterogeneity in different processors and achieve improved energy efficiency. © 2011 IEEE.

关键词： Energy efficiency

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Data parallelism exploiting for H.264 encoder

Data parallelism exploiting for H.264 encoder

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International Conference on Multimedia and Signal processing

作者： Wen, Mei Ren, Ju Wu, Nan Su, Huayou Xun, Changqing Zhang, Chunyuan Parallel and Distributed Processing Laboratory National University of Defense Technology Changsha China

ISBN: (纸本)9780769543567

Real-time H.264 encoding of high-definition (HD) video (up to 1080p) is a challenge workload to most existing programmable processors. Instead, the novel programmable parallel processors such as stream processor, Graphic processor unit (GPU) and DSP offer a different and very promising technology for these demands. Thus, parallel computing for H.264 encoding on these processors is becoming a hot research point. It's challenged, because most emerging parallel processors focus on supporting Data Level parallel (DLP), while the dependency inherently existing in traditional H.264 encoding algorithm significantly restricts exploiting DLP. Facing the challenge, this paper presents data parallel processing methods for key modules of H.264 encoder which can eliminate the dependency restriction. The result shows that key modules including Intra-prediction, Inter-prediction and CAVLC achieve significant speedup on stream processor by using these data parallel processing methods.© 2011 IEEE.

关键词： parallel processing systems

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Approximating quantified SMT-solving with SAT

Approximating quantified SMT-solving with SAT

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International Conference on Secure Software Integration and Reliability Improvement Companion

作者： Fu, Xianjin Liu, Wanwei Li, Jing National Laboratory for Parallel and Distributed Processing National University of Defense Technology Changsha 410073 China

ISBN: (纸本)9780769544540

Satisfiability Modulo Theories (SMT) is an extension of SAT towards FOL. SMT solvers have proven highly scalable and efficient for problems based on some ground theorems. However, SMT problems involving quantifiers and combination of theorems is a long-standing challenge, which has been a major bottleneck of practical application of SMT solvers in some fields. We reveal a decidable fragment of FOL involving quantifiers, which could not be solved by SMT solvers such as Z3, CVC3, etc., and show how to convert them into model checking problems. © 2011 IEEE.

关键词： Model checking

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Special-purposed VLIW architecture for IEEE-754 quadruple precision elementary functions on FPGA

Special-purposed VLIW architecture for IEEE-754 quadruple pr...

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29th IEEE International Conference on Computer Design 2011, ICCD 2011

作者： Lei, Yuanwu Dou, Yong Shen, Li Zhou, Jie Guo, Song National Laboratory for Parallel and Distributed Processing National University of Defense Technology Changsha 410073 China

ISBN: (纸本)9781457719523

This work explores the feasibility to implement IEEE-754-2008 standard quadruple precision (Quad) elementary functions on recent FPGAs with plenty of embedded memories and DSP blocks. First, we analysis the implementation algorithm of Quad elementary functions in detail. Then, we present a special-purpose Very Large Instruction Word (VLIW) architecture for Quad elementary function (QE-Processor). The proposed processor uses a unified hardware structure, equipped with multiple basic arithmetic units, to implement various Quad algebraic and transcendental functions, in which several tradeoffs between latency and resource usage are carefully planned to avoid unbalanced resource utilization. The performance is improved through the explicitly parallel technology of custom VLIW instruction. Finally, we create a prototype of QE-Processor into Xilinx Virtex-5 and Virtex-6 FPGA chips. The experimental results show that our design can guarantee that the percentage of correct rounding is more than 99.9%. Moreover, the FPGA implementation on Virtex-6 XC6VLX760-2FF1760 FPGA, running at 220 MHz, outperforms the parallel software approach based on OpenMP running on an Intel Xeon E5620 CPU at 2.40GHz by a factor of 13X-20X for special function applications in Boost library. © 2011 IEEE.

关键词： Field programmable gate arrays (FPGA)

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Global EDF-based online, energy-efficient real-time scheduling in multi-core platform

Global EDF-based online, energy-efficient real-time scheduli...

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IEEE International Conference on Computer Science and Automation Engineering

作者： Zhang, Dongsong Chen, Fangyuan Jin, Shiyao National Laboratory of Parallel and Distributed Processing College of Computer National University of Defense Technology Changsha China

ISBN: (纸本)9781424487257

As the energy consumption becomes increasingly prominent, how to meet time constraints while reducing the energy consumption as much as possible is a fundamental problem of the real-time scheduling in multi-core systems. Most of the existing energy-efficient scheduling approaches make assumptions on the properties of the scheduled tasks. In general, the properties of a task are unknown in advance until the task arrives. Thus, these approaches for deterministic tasks are not suitable to the general tasks. To schedule general tasks without prior knowledge of their properties, we propose an online and energy-efficient scheduling algorithm, based on Global Earliest Deadline First, for hard real-time tasks in multi-core processor platform. We propose a novel approach to decrease the execution frequency of tasks, and achieve a reasonable compromise between the time constraint and saved energy. This is ensured by utilizing the slack time of tasks and the dynamic voltage/frequency scaling techniques. The evaluation results show that our algorithm is well applied to the two types of dynamic voltage/frequency scaling techniques, and out-performs the Global EDF algorithm in terms of the saved energy. Specifically, our algorithm improves the saved energy of the Global EDF algorithm by at most 10% to 15% under real discrete dynamic voltage/frequency scaling levels. © 2011 IEEE.

关键词： Real time systems

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Storage allocation for redundancy scheme in reliability-aware cloud systems

Storage allocation for redundancy scheme in reliability-awar...

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2011 IEEE 3rd International Conference on Communication Software and Networks, ICCSN 2011

作者： Huang, Zhen Yuan, Yuan Peng, Yuxing National Laboratory of Parallel and Distributed Processing Computer Department National University of Defense Technology Changsha China

ISBN: (纸本)9781612844855

As the burst increasing of created and demand on information and data, the efficient solution on storage management is highly required in the cloud storage systems. As an important component of management, storage allocation scheme aims to use a low redundancy and also to achieve a high reliability. However, the two aims are hard to be unified. Considering the practical situation of Cloud systems, we propose a systematic storage allocation scheme to touch them both. And we also study the impact of many factors to the data reliability. © 2011 IEEE.

关键词： Information management

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parallelization of the training for face detection with transactional memory

Parallelization of the training for face detection with tran...

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2011 International Conference on Automation and Robotics, ICAR 2011

作者： Zeng, Kun Key Laboratory and Technology for National Defence of Parallel and Distributed Processing School of Computer National Univiersity of Defense Technology ChangSha Hunan China

ISBN: (纸本)9783642256455

The development of multi-core processor makes the parallelization of traditional sequential algorithms increasingly important. Meanwhile, transactional memory serves a good parallel programming model. This paper takes the advantage of software transactional memory to parallelize the Multi-Exit Asymmetric Adaboost algorithm for face detection. The parallel version is evaluated on three different implementations of software transactional memory. The experiment results show that the transactional memory based parallelization outperforms the traditional lock based approach. A speedup of nearly seven is achieved on a eight-core machine on an eight-core system. © 2011 Springer-Verlag.

关键词： Face recognition

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Impact of imprecise programming of memristor on building hardware neural network

Impact of imprecise programming of memristor on building har...

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2nd Annual Conference on Electrical and Control Engineering, ICECE 2011

作者： Zhu, Xuan National Laboratory for Parallel and Distributed Processing School of Computer National University of Defense Technology ChangSha China

ISBN: (纸本)9781424481637

The application of memristor in building hardware neural network has accepted widespread interests, and may bring novel opportunities to neural computing. However, due to the limitation of programming precision, the conductance of memristor which represents stored information may deviate from theoretical value, and thus bring error to the neural computing results. In this paper, we analyze the impact of imprecise programming on building hardeware neural network through Monte Carlo simulation on feedback layer model. The results show that the fault-tolerance ability of neural network could well adapt to these errors, which further proves the potential of building neural networks using memristors. © 2011 IEEE.

关键词： Errors

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